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N82C55AN Schematic ( PDF Datasheet ) - Integral

Teilenummer N82C55AN
Beschreibung IN82C55AN
Hersteller Integral
Logo Integral Logo 




Gesamt 21 Seiten
N82C55AN Datasheet, Funktion
IN82C55AN
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard
IN82C55AN general purpose programmable I/O device which is designed for use with all
Intel and most other microprocessors. It provides 24 I/O pins which may be individually
programmed in 2 groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs
or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output.
3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2
is a strobed bi-directional bus configuration.
FEATURES
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Compatible with all Intel and Most Other Microprocessors
High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188
24 Programmable I/O Pins
Low Power CHMOS
Completely TTL Compatible
Control Word Read-Back Capability
Direct Bit Set/Reset Capability
2.5mA DC Drive Capability on all I/O Port Outputs
Available in 40-Pin DIP
Available in EXPRESS
ƒ Standard Temperature Range
ƒ Extended Temperature Range
GROUP
A
CONTROL
D7-D0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
RD
WR
A1
A0
Reset
CS
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
Figure 1
GROUP
A
PORT
A
(8)
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
GROUP
B
PORT
B
(8)
PA7-PA0
PC7-PC4
PC3-PC0
PB7-PB0
PA3
PA2
PA1
PA0
RD
CS
VSS
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1. 40
2. 39
3. 38
4. 37
5. 36
6. 35
7. 34
8. 33
9. 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
Figure 2
PA4
PA5
PA6
PA7
WR
Reset
D0
D1
D2
D3
D4
D5
D6
D7
VCC
PB7
PB6
PB5
PB4
PB3
1






N82C55AN Datasheet, Funktion
www.DataSheet4U.com
IN82C55AN
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
Figure 6. Mode Definition Format
The mode definitions and possible mode combinations may seem confusing at first but after a cursory review
of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has
taken into account things such as efficient PC board layout, control signal definition vs PC layout and
complete functional flexibility to support almost any peripheral device with no external logic. Such design
represents the maximum use of the available pins.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature reduces
software requirements in Control-based applications.
When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit
Set/Reset operation just as if they were data output ports.
D7 D6 D5 D4 D3 D2 D1 D0
DON’T
CARE
BIT SET/RESET
1 = SET
0 =RESET
BIT SELECT
01234567
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
BIT SET/RESET FLAG
0 = ACTIVE
Figure 7. Bit Set/Reset Format
6

6 Page









N82C55AN pdf, datenblatt
IN82C55AN
STB
tST
tSIB
IBF
INTR
tSIT
tRIT
tRIB
RD
tPH
INPUT FROM
PERIPHERAL
tPS
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Figure 9. MODE 1 (Strobed Input)
Output Control Signal Definition
OBF (Output Buffer Full F/F). The OBF output will go “low” to indicate that the CPU has written data out to
the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by ACK Input being
low.
ACK (Acknowledge Input). A “low” on this input informs the IN82C55AN that the data from Port A or Port B
has been accepted. In essence, a response from the peripheral device indicating that it has received the
data output by the CPU.
INTR (Interrupt Request). A “high” on this output can be used to interrupt the CPU when an output device
has accepted data transmitted by the CPU. INTR is set when ACK is a “one”, OBF is a “one” and INTE is a
“one”. It is reset by the falling edge of WR .
INTE A
Controlled by bit set/reset of PC6.
INTE B
Controlled by bit set/reset of PC2.
MODE 1 (PORT A)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1/0 X X X
PC6,7
1 = INPUT
0 = OUTPUT
WR
PA7-PA0
INTE
A
PC6
PC7
8
ACKA
OBFA
PC3
PC4,5
INTRA
2
MODE 1 (PORT B)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 XXXX1 0 X
PB7-PB0
INTE
B
PC2
PC1
8
ACKB
OBFB
WR PC0 INTRB
Figure 10. MODE 1 Output
12

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