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PDF PI6C3Q991 Data sheet ( Hoja de datos )
| Número de pieza | PI6C3Q991 | |
| Descripción | (PI6C3Q991 / PI6C3Q993) 3.3V Programmable Skew PLL Clock Driver | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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PI6C3Q991, PI6C3Q9931122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V Programmable Skew PLL Clock Driver
SuperClock®
Features
PI6C3Q99X family provides following products:
PI6C3Q991: 32-pin PLCC version
PI6C3Q993: 28-pin QSOP version
Inputs are 5V I/O Tolerant
4 pairs of programmable skew outputs
www.DataSheLeot4wUs.ckoemw: 200ps same pair; 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75 MHz to 85 MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: < 200ps peak-to-peak
Industrial temperature range
Pin-to-pin compatible with IDT QS5V991 and QS5V993
Available in 32-pin PLCC and 28-pin QSOP
Description
The PI6C3Q99X family is a high fanout 3.3V PLL-based clock driver
intended for high performance computing and data-communica-
tions applications. A key feature of the programmable skew is the
ability of outputs to lead or lag the REF input signal. The PI6C3Q991
has 8 programmable skew outputs in 4 banks of 2, while the
PI6C3Q993 has 6 programmable skew outputs and 2 zero skew
outputs. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchro-
nously enabled. However, if GND/sOE is held high, all the outputs
except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when
the V CCQ /PE is held high, all the outputs are synchronized with the
positive edge of the REF clock input. When VCCQ /PE is held low,
all the outputs are synchronized with the negative edge of REF. Both
devices have LVTTL outputs with 12mA balanced drive outputs.
Pin Configurations
PI6C3Q991
3F1
4F0
4F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7 27
8 32-Pin
9J
10
26
25
24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
PI6C3Q993
REF
VCCQ
FS
3F0
3F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
3Q1
3Q0
VCCN
FB
1 28
2 27
3 26
4 25
5 24
6 28-Pin 23
7 Q 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
GND
TEST
2F1
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
2Q0
2Q1
1 PS8449A 10/09/00
1 page  
PI6C3Q991, PI6C3Q993
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221132233.34455V667788P9900r11o22g3344r55a6677m8899m001122a3344b55l66e7788S9900k11e2211w223344P5566L7788L9900C1122l33o4455c66k778899D0011r22i33v4455e66r7788S9900u11p2211e22r33C4455l66o7788c99k0011®22
Table 6. DC Characteristics Over Operating Range
Symbol
Parameter
Test Condition
Min.
Max.
VIH
Input HIGH Voltage
Guaranteed Logic HIGH
(REF, FB inputs only)
2.0
VIL
VIHH
www.DataSheet4UV.cIMomM
VILL
IIN
I3
IPU
IPD
Input LOW Voltage
Input HIGH Voltage(1)
Input MID Voltage(1)
Input LOW Voltage(1)
Input Leakage Current (REF,
FB inputs only)
3-Level Input DC Current
(TEST, FS, nF1:0)
Input Pull-Up Current
(VCCQ/PE)
Input Pull-Down Current
(GND/sOE)
Guaranteed Logic LOW
(REF, FB inputs only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN = VCC or GND,
VCC = Max.
VIN = VCC
VIN = VCC/2
VIN = GND
HIGH Level
MID Level
LOW Level
VCC = Max., VIN = GND
VCC = Max., VIN = VCC
VCC 0.6
VCC/2 0.3
0.8
VCC/2 +0.3
0.6
5
200
50
200
100
100
VOH
Output HIGH Voltage
VCC = Min., IOH = 12mA
2.2
VOL
Output LOW Voltage
VCC = Min., IOL = 12mA
0.55
Note:
1. These inputs are normally wired to VCC , GND, or unconnected. Internal termination resistors bias unconnected inputs
to VCC/2. If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require
an additional tLOCK time before all datasheet limits are achieved.
Units
V
µA
V
Table 7. Power Supply Characteristics
Symbol
Parameter
Test Condition
ICCQ
∆ICC
ICCD
IC
IC
IC
Quiescent Power Supply Current
VCC = Max., TEST = Mid., REF = LOW,
GND/sOE = LOW, All outputs unloaded
Power Supply Current per Input HIGH(1) VCC = Max., VIN = 3.0V
Dynamic Power Supply Current per Output(1) VCC = Max., CL = 0pF
Total Power Supply Current(1)
VCC = 3.3V, FREF = 20 MHz, CL = 160pF(2)
Total Power Supply Current(1)
VCC = 3.3V, FREF = 33 MHz, CL = 160pF(2)
Total Power Supply Current(1)
VCC = 3.3V, FREF = 66 MHz, CL = 160pF(2)
Notes:
1. Guaranteed by characterization but not production tested.
2. For 8 outputs each loaded with 20pF.
Typ. Max. Units
8.0 15 mA
1.0 30
µA
55 90 µA/MHz
29
42 mA
76
5 PS8449A 10/09/00
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI6C3Q991.PDF ] | |
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| PI6C3Q991 | (PI6C3Q991 / PI6C3Q993) 3.3V Programmable Skew PLL Clock Driver | Pericom Semiconductor Corporation |
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