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PDF CY7C185D Data sheet ( Hoja de datos )
| Número de pieza | CY7C185D | |
| Descripción | 64K (8K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY7C185D
64K (8K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C185
• High speed
— tAA = 10 ns
• Low active power
www.DataSheet4U—.coImCC = 60 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 3 mA
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Lead (Pb)-Free Packages
Functional Description[1]
The CY7C185D is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and three-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.The CY7C185D is in a standard 28-pin
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
CE1
CE2
WE
OE
INPUT BUFFER
256 x 32 x 8
ARRAY
POWER
COLUMN DECODER DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 CE2
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE1
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05466 Rev. *C
Revised January 10, 2005
1 page  
PRELIMINARY
CY7C185D
Switching Characteristics Over the Operating Range (continued)[6]
Parameter
Write Cycle[9]
tWC
tSCE1
tSCE2
tAW
tHA
www.DataSheet4tSUA.com
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Write Cycle Time
CE1 LOW to Write End
CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[7]
WE HIGH to Low Z
7C185D-10
Min. Max.
7C185D-12
Min. Max.
10 12
8 10
8 10
7 10
00
00
7 10
67
00
66
33
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current Non-L, Com’l / Ind’l
tCDR [4]
tR[10]
L-Version Only
Chip Deselect to Data Retention Time
Operation Recovery Time
Data Retention Waveform
Conditions
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
7C185D-15
Min. Max.
15
12
12
12
0
0
12
8
0
7
3
Min.
2.0
0
tRC
Max.
3
1.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
V
mA
mA
ns
ns
DATA RETENTION MODE
VCC
4.5V
VDR > 2V
4.5V
tCDR
tR
CE
Switching Waveforms
Read Cycle No.1[11,12]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
DATA VALID
Notes:
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
11. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
12. WE is HIGH for read cycle.
Document #: 38-05466 Rev. *C
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