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PDF ST62T45B Data sheet ( Hoja de datos )

Número de pieza ST62T45B
Descripción 8-BIT OTP/EPROM MCU
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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R ST62T45B/E45B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
www.DataSheet4Us.co-m40 to +85°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 128 bytes
s Data EEPROM: 128 bytes
s User Programmable Options
s 19 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
– LCD segments (8 combiport lines)
s 4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s Two 8-bit Timer/Counter with 7-bit
programmable prescaler
s Digital Watchdog
s 8-bit A/D Converter with 7 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s LCD driver with 24 segment outputs, 4
backplane outputs and selectable multiplexing
ratio.
s 32kHz oscillator for stand-by LCD operation
s On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
s One external Non-Maskable Interrupt
s ST6245-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T45B
ST62E45B
OTP
(Bytes)
3884
EPROM
(Bytes)
-
3884
I/O Pins
11 to 19
11 to 19
PQFP52
CQFP52W
(See end of Datasheet for Ordering Information)
Rev. 2.3
March 1998
1/72
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ST62T45B pdf
ST62T45B/E45B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T45B and ST62E45B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de-
vices are based on a building block approach: a
www.DataSheet4U.com
Figure 1. Block Diagram
common core is surrounded by a number of on-
chip peripherals.
The ST62E45B is the erasable EPROM version of
the ST62T45B device, which may be used to em-
ulate the ST62T45B device, as well as the respec-
tive ST6245B ROM devices.
T EST/VPP
NMI
TES T
8-BIT
A/D CONVERTER
INT ERRUPT
PR OGRAM
Memory
3884 bytes
DATA ROM
USER
SELECTABLE
DATA RAM
12 8 Bytes
DATA EEPROM
128 Bytes
PC
STAC K LEVEL 1
STAC K LEVEL 2
STAC K LEVEL 3
STAC K LEVEL 4
STAC K LEVEL 5
STAC K LEVEL 6
8 BIT CORE
POWER OSCILLATOR RESET
SUPPLY
VDD VSS OSCin OSCout RESET
(VPP on EPROM/OTP versions only)
PORT A
PORT B
PORT C
LCD DRIVER
OSC 32kHz
TIMER 2
TIMER 1
DIGITA L
WATC HDOG
SPI (SERIAL
PERI PHERAL
INT ERFACE)
PA 5..PA7/Ain
PB 0..PB3/Ain
PB4/20mA Sink
PB5/Scl/20mA Sink
PB6/Sin/20mA Sink
PB7/Sout/20mA Sink
PC0..PC7/S33..S40
S17..S32
COM1..COM4
VLCD
VLCD1/3
VLCD2/3
OSC32in
OSC32out
TIMER
VR01994
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ST62T45B arduino
ST62T45B/E45B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
The Data Read-Only Memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be-
tween address 0000h and 1FFFh (top memory ad-
dress depends on the specific device). All the pro-
gram memory can therefore be used to store either
instructions or read-only data. Indeed, the window
www.DataSheet4Uc.caonm be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM loca-
tion in the Data Space, it is however a write-only
register and therefore cannot be accessed using
single-bit operations. This register is used to posi-
tion the 64-byte read-only data window (from ad-
dress 40h to address 7Fh of the Data space) in
program memory in 64-byte steps. The effective
address of the byte to be read as data in program
memory is obtained by concatenating the 6 least
significant bits of the register address given in the
instruction (as least significant bits) and the con-
tent of the DWR register (as most significant bits),
as illustrated in Figure 5 below. For instance,
when addressing location 0040h of the Data
Space, with 0 loaded in the DWR register, the
physical location addressed in program memory is
00h. The DWR register is not cleared on reset,
therefore it must be written to prior to the first ac-
cess to the Data read-only memory window area.
Address: 0C9h — Write Only
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 7, 6 = Not used.
Bit 5-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service rou-
tine, an image of the register must be saved in a
RAM location, and each time the program writes
to the DWR, it must also write to the image regis-
ter. The image register must be written first so
that, if an interrupt occurs between the two instruc-
tions, the DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
DATA ROM
13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS
WINDOW REGISTER 7 6 5 4 3 2 1 0
READ
CONTENTS
(DWR)
5 4 3 2 1 0 DATA SPACE ADDRES:S
01
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h
10 10 0 0
01
0
110
0
1
DATA SPACE ADDRES:S
59h
ROM
ADDRESS:A19h
10 10 0 0 0 110 0 1
VR01573C
11/72
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