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PDF ST62E28C Data sheet ( Hoja de datos )
| Número de pieza | ST62E28C | |
| Descripción | 8-BIT MCUs | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ST62T28C/E28C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
www.DataSheet4Us.co-m40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s User Programmable Options
s 20 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 12 analog inputs
s 8-bit Asynchronous Peripheral Interface
(UART)
s 8-bit Synchronous Peripheral Interface (SPI)
s On-chip Clock oscill ator can be driven by
Quartz Crystal, Ceramic resonator or RC
network
s Oscillator Safe Guard
s Low Voltage Detector for safe Reset
s One external Non-Maskable Interrupt
s ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T28C
ST62E28C
OTP
(Bytes)
7948
EPROM
(Bytes)
-
7948
I/O Pins
20
20
November 1999
PDIP28
PS028
SS0P28
CDIP28W
(See end of Datasheet for Ordering Information)
Rev. 2.8
1/84
1
1 page  
ST62T28C/E28C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T28C and ST62E28C devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de-
vices are based on a building block approach: a
common core is surrounded by a number of on-
chip peripherals.
www.DataSheet4U.com
The ST62E28C is the erasable EPROM version of
the ST62T28C device, which may be used to em-
ulate the ST62T28C device, as well as the respec-
tive ST6228C ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
Figure 1. Block Diagram
fined in the programmable option byte of the OTP/
EPROM versions.OTP devices offer all the advan-
tages of user programmability at low cost, which
make them the ideal choice in a wide range of ap-
plications where frequent code changes, multiple
code versions or last minute programmability are
required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer, with
1 input capture channel, capability, a serial asyn-
chronous port interface (UART), a synchronous
serial port interface, an 8-bit A/D Converter with 12
analog inputs and a Digital Watchdog timer, mak-
ing them well suited for a wide range of automo-
TE ST/VPP
NMI
TEST
8-BIT
A/D CONVERTER
INTERRUPT
PROGR AM
Memory
7948 bytes
DATA ROM
USE R
SELECTABLE
DATA RAM
192 Bytes
PORT A
PORT B
PORT C
PORT D
UART
PA0..PA1 / 20 mA Sink
PA2/ARTIMout / 20 mA Sink
PA3/ARTIMin/ 20 mA Sink
PA4..PA5/20 mA Sink
PB4.. PB6/Ain
PC 4..PC5/A in
PC6..PC7/20 mA Sink
P D1/Ain/ Scl
P D2/Ain/ Sin
P D3/Ain/ Sout
P D4/Ain/ RXD1
P D5/Ain/ TXD1
PD6,PD7/Ain
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER OSCILLATOR RESET
SUPP LY
A UTORELOA D
TIMER
TIMER
SPI
DIGITAL
WATCHD OG
VDD VSS OSCin OSCout RESET
(VPP on EPROM/OTP versions only)
TIMER
VR01823F
5/84
5
5 Page 
ST62T28C/E28C
MEMORY MAP (Cont’d)
1.3.6 Data RAM Bank Register (DRBR)
Address: CBh — Write only
7
- - - DRBR4 DRBR3 -
-
0
-
Bit 7-5 = These bits are not used
www.DataSheet4UPB.caiotmg4e
- DRBR4.
2.
This
bit,
when
set,
selects
RAM
Bit 3 - DRBR3. This bit, when set, selects RAM
Page 1.
Bit 2.0 These bits are not used.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address CBh of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space location at the address CBh; never-
theless it is a write only register that cannot be ac-
cessed with single-bit operations. This register is
used to select the desired 64-byte RAM bank of
the Data Space. The number of banks has to be
loaded in the DRBR register and the instruction
has to point to the selected location as if it was in
bank 0 (from 00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes:
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 5. Data RAM Bank Register Set-up
DRBR
00h
01h
02h
08h
10h
other
ST62T28C/E28C
None
Reserved
Reserved
RAM Page 1
RAM Page 2
Reserved
11/84
11
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