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46V32M16 Schematic ( PDF Datasheet ) - Micron Technology

Teilenummer 46V32M16
Beschreibung MT46V32M16
Hersteller Micron Technology
Logo Micron Technology Logo 




Gesamt 68 Seiten
46V32M16 Datasheet, Funktion
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
www.DataSheetc4aUp.ctoumre (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• x16 has programmable IOL/IOV.
• Concurrent auto precharge option is supported
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
OPTIONS
MARKING
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8
32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
• Plastic Package – OCPL
66-pin TSOP (standard 22.3mm length) TG
(400 mil width, 0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)1
7.5ns @ CL = 2.5 (DDR266B)2
10ns @ CL = 2 (DDR200)2
-75Z
-75
-8
• Self Refresh
Standard
none
Low Power
L
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
x4 x8 x16
VDD
VDD
VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VssQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VssQ
NC NC DQ7
NC NC NC
VDDQ VDDQ VDDQ
NC NC LDQS
NC NC NC
VDD
VDD
VDD
DNU DNU DNU
NC NC LDM
WE# WE# WE#
CAS# CAS# CAS#
RAS# RAS# RAS#
CS# CS# CS#
NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
x16 x8 x4
66 VSS VSS VSS
65 DQ15 DQ7 NC
64 VSSQ VSSQ VSSQ
63 DQ14 NC NC
62 DQ13 DQ6 DQ3
61 VDDQ VDDQ VDDQ
60 DQ12 NC NC
59 DQ11 DQ5 NC
58 VSSQ VSSQ VSSQ
57 DQ10 NC NC
56 DQ9 DQ4 DQ2
55 VDDQ VDDQ VDDQ
54 DQ8 NC NC
53 NC
NC NC
52 VSSQ VSSQ VSSQ
51 UDQS DQS DQS
50 DNU DNU DNU
49
VREF
VREF VREF
48 VSS VSS VSS
47 UDM DM DM
46 CK# CK# CK#
45 CK
CK CK
44 CKE CKE CKE
43 NC
NC NC
42 A12 A12 A12
41 A11 A11 A11
40 A9
A9 A9
39 A8
A8 A8
38 A7
A7 A7
37 A6
A6 A6
36 A5
A5 A5
35 A4
A4 A4
34 VSS VSS VSS
Configuration
RefreshCount
RowAddressing
BankAddressing
ColumnAddressing
128 Meg x 4
32 Meg x 4 x 4banks
8K
8K(A0–A12)
4(BA0,BA1)
4K(A0–A9,A11,A12)
64 Meg x 8
16 Meg x 8 x 4 banks
8K
8K(A0–A12)
4(BA0,BA1)
2K(A0–A9, A11)
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K(A0–A12)
4(BA0,BA1)
1K(A0–A9)
KEY TIMING PARAMETERS
SPEED
GRADE
-75
-75
-8
CLOCK RATE
CL = 2** CL = 2.5**
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
125 MHz
DATA-OUT ACCESS DQS-DQ
WINDOW* WINDOW SKEW
2.5ns
2.5ns
3.4ns
±0.75ns
±0.75ns
±0.8ns
+0.5ns
+0.5ns
+0.6ns
*Minimum clock rate @ CL = 2 (-8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.






46V32M16 Datasheet, Funktion
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 16
CKE
CK#
CK
www.DataSheet4UCS.#com
WE#
CAS#
RAS#
CONTROL
LOGIC
REFRESH
COUNTER
13
BANK3
BANK2
BANK1
A0-A12,
BA0, BA1
MODE REGISTERS
13
13
15
ADDRESS
REGISTER
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 512 x 32)
SENSE AMPLIFIERS
16,384
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
9
10 COUNTER/
LATCH
1
I/O GATING
DM MASK LOGIC
512
(x32)
COLUMN
DECODER
CK
16
32 READ
MUX
LATCH 16
DATA
DLL
16
DQS
GENERATOR
DRVRS
2
COL0
INPUT
DQS
32 REGISTERS
MASK
WRITE
32 FIFO
&
DRIVERS
4
32
ck ck
out in DATA
2
2
16
16
2
2
2
RCVRS
16
16
16
CK
COL0
2
DQ0 -
DQ15,
LDM,
UDM
LDQS
UDQS
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01
6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

6 Page









46V32M16 pdf, datenblatt
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
EXTENDED MODE REGISTER
The extended mode register controls functions be-
yond those controlled by the mode register; these ad-
ditional functions are DLL enable/disable and
output drive strength. These functions are controlled
via the bits shown in Figure 3. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power. The en-
www.DataShaeebtl4iUn.gcoomf the DLL should always be followed by a LOAD
MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
The normal drive strength for all outputs are speci-
fied to be SSTL2, Class II. The x16 supports an option
for reduced drive. This option is intended for the sup-
port of the lighter load and/or point-to-point environ-
ments. The selection of the reduced drive strength will
alter the DQs and DQSs from SSTL2, Class II drive
strength to a reduced drive strength, which is approxi-
mately 54% of the SSTL2, Class II drive strength.
The Micron (32Meg x16) device supports a
programmable drive strength option.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode
01 11
Operating Mode
QFC# DS DLL Register (Ex)
E0 DLL
0 Enable
1 Disable
E12 Drive Strength
0 Normal
1 Reduced
E23 QFC# Function
0 Disabled
Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
0 0 0 0 0 0 00 0 0
– – – – – – –– – –
E2, E1, E0
Valid
Operating Mode
Reserved
Reserved
NOTE:
1. E14 and E13 (BA0 and BA1) must be 1, 0to select the
Extended Mode Register (vs. the base Mode Register).
2. The reduced drive strength option is not supported on the x4
and x8 versions, and is only available on the x16 version.
3. The QFC# option is not supported.
Figure 3
Extended Mode Register Definition
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

12 Page





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