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PDF MPC954 Data sheet ( Hoja de datos )
| Número de pieza | MPC954 | |
| Descripción | LOW VOLTAGE PLL CLOCK DRIVER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MPC954 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC954 is a 3.3V compatible, PLL based zero delay buffer
targeted for high performance clock tree designs. With 11 outputs at
frequencies of up to 100MHz and output skews of 200ps the MPC954 is
ideal for the most demanding clock tree designs. The devices employ a
fully differential PLL design to minimize cycle–to–cycle and phase jitter.
• Fully Integrated PLL
www.DataShe•et4OUu.ctpomut Frequency up to 100MHz
• Outputs Disable in High Impedance
• TSSOP Packaging
• 50ps Cycle–to–Cycle Jitter Typical
The analog VCC pin of the device also serves as a PLL bypass select
pin. When driven low the VCCA pin will route the REF_CLK input around
the PLL directly to the outputs. The OE input is a logic enable for all of the
outputs except QFB. A low on the OE pin forces Q0–Q9 to a logic low
state.
The MPC954 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS or LVTTL compatible levels
while the outputs provide LVCMOS levels with the ability to drive
terminated 50Ω transmission lines. The output impedance of the MPC954
is 10W , therefore for series terminated 50Ω lines, each of the MPC954
outputs can drive two traces giving the device an effective fanout of 1:22.
The device is packaged in a 24–lead TSSOP package to provide the
optimum combination of board density and performance.
Order this document
by MPC954/D
MPC954
LOW VOLTAGE
PLL ZERO DELAY BUFFER
DT SUFFIX
24–LEAD TSSOP PACKAGE
CASE 948H–01
(Int pull down)
REF_CLK
(Int pull down)
FB_CLK
VCCA
OE
PLL
Figure 1. Block Diagram
Q0
Q9
QFB
06/00
© Motorola, Inc. 2000
1
REV 1
1 page  
MPC954
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 43Ω || 43Ω
Ro = 7Ω
VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)
= 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.80V. It will then increment
www.DataShetteortip4wUad.rcedolsamythe(inquthieisscceanste3.40.V0nins)s. teps separated by one round
3.0
OutA
2.5 tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
0.5
0
2 4 6 8 10 12 14
TIME (nS)
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC954
OUTPUT
BUFFER
7Ω
RS = 22Ω ZO = 50Ω
RS = 22Ω ZO = 50Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
ECLinPS and ECLinPS Lite
DL140 — Rev 3
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MPC954.PDF ] | |
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