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UDA1350AH Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UDA1350AH
Beschreibung IEC 958 audio DAC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
UDA1350AH Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
UDA1350AH
IEC 958 audio DAC
Preliminary specification
File under Integrated Circuits, IC01
1999 Dec 16






UDA1350AH Datasheet, Funktion
Philips Semiconductors
IEC 958 audio DAC
7 PINNING
SYMBOL
RESET
VDDD(C)
VSSD
VSSD(C)
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L3DATA
L3CLOCK
DATAI
BCKI
WSI
L3MODE
n.c.
MUTE
SELCHAN
n.c.
SPDIF0
SPDIF1
VDDA(DAC)
VOUTL
SELCLK
SELSPDIF
LOCK
VOUTR
TC
Vref
VSSA(DAC)
VSSA
VDDA
n.c.
CLKOUT
PREEM1
VSSA(PLL)
VDDA(PLL)
BCKO
TEST1
SELSTATIC
DATAO
WSO
n.c.
TEST2
n.c.
1999 Dec 16
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Preliminary specification
UDA1350AH
TYPE(1)
DISD
DS
DGND
DGND
DIOS
DIS
DISD
DISD
DISD
DIS
DID
DID
AI
AI
AS
AO
DID
DIU
DO
AO
DID
A
AGND
AGND
AS
DO
DO
AGND
AS
DO
DIU
DIU
DO
DO
DISD
DESCRIPTION
reset input
digital supply voltage for core
digital ground
digital ground for core
L3 interface data input and output
L3 interface clock input
I2S-bus data input
I2S-bus bit clock input
I2S-bus word select input
L3 interface mode input
not connected
mute control input
IEC 958 channel selection input
not connected
IEC 958 channel 0 input
IEC 958 channel 1 input
analog supply voltage for DAC
DAC left channel analog output
clock source for PLL selection input
IEC 958 data selection input
SPDIF and PLL lock indicator output
DAC right channel analog output
test pin; must be connected to digital ground (VSSD)
DAC reference voltage
analog ground for DAC
analog ground
analog supply voltage
not connected
clock output (256fs)
IEC 958 input pre-emphasis output 1
analog ground for PLL
analog supply voltage for PLL
I2S-bus bit clock output
test pin 1: must be connected to digital supply voltage (VDDD)
static pin control selection input
I2S-bus data output
I2S-bus word select output
not connected
test pin 2; must be connected to digital ground (VSSD)
not connected
6

6 Page









UDA1350AH pdf, datenblatt
Philips Semiconductors
IEC 958 audio DAC
Preliminary specification
UDA1350AH
8.5.3 AUDIO FEATURE PROCESSOR
The audio feature processor automatically provides
de-emphasis for the IEC 958 data stream in the static pin
control mode and default mute at start-up in the L3 control
mode.
When used in the L3 control mode it provides the following
additional features:
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Volume control using 6 bits
Bass boost control using 4 bits
Treble control using 2 bits
Mode selection of the sound processing bass boost and
treble filters: flat, minimum and maximum
Soft mute control with raised cosine roll-off
De-emphasis selection of the incoming data stream for
fs = 32.0, 44.1 and 48.0 kHz.
8.5.4 INTERPOLATOR
The UDA1350AH includes an on-board interpolating filter
which converts the incoming data stream from 1fs to 128fs
by cascading a recursive filter and a FIR filter.
Table 2 Interpolator characteristics
PARAMETER
Pass-band ripple
Stop band
Dynamic range
DC gain
CONDITIONS
0 to 0.45fs
>0.65fs
0 to 0.45fs
VALUE (dB)
±0.03
50
115
3.5
8.5.5 NOISE SHAPER
The third-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
8.5.6 FILTER STREAM DAC
The Filter Stream DAC (FSDAC) is a semi-digital
reconstruction filter that converts the 1-bit data stream of
the noise shaper to an analog output voltage. The filter
coefficients are implemented as current sources and are
summed at virtual ground of the output operational
amplifier. In this way very high signal-to-noise
performance and low clock jitter sensitivity is achieved. A
post filter is not needed due to the inherent filter function of
the DAC. On-board amplifiers convert the FSDAC output
current to an output voltage signal capable of driving a line
output.
The output voltage of the FSDAC is scaled proportionally
with the power supply voltage.
1999 Dec 16
12

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