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Número de pieza | CY7C1412JV18 | |
Descripción | (CY7C14xxJV18) SRAM 2-Word Burst Architecture | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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No Preview Available ! CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
36-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 267 MHz clock for high bandwidth
■ 2-word burst on all accesses
www.DataSh■eeDt4oUu.bcloemData Rate (DDR) interfaces on both read and write ports
(data transferred at 534 MHz) at 267 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR™-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
■ Operates like a QDR-I device with 1 cycle read latency in DLL
off mode
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1410JV18 – 4M x 8
CY7C1425JV18 – 4M x 9
CY7C1412JV18 – 2M x 18
CY7C1414JV18 – 1M x 36
Functional Description
The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and
CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has data outputs to support read
operations and the write port has data inputs to support write
operations. QDR-II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR-II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are provided with DDR interfaces. Each address location
is associated with two 8-bit words (CY7C1410JV18), 9-bit words
(CY7C1425JV18), 18-bit words (CY7C1412JV18), or 36-bit
words (CY7C1414JV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
267 MHz
267
x8 1330
x9 1330
x18 1370
x36 1460
250 MHz
250
1200
1200
1230
1290
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-12561 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 10, 2007
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1 page CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Pin Configuration
The pin configuration for CY7C1410JV18, CY7C1412JV18, and CY7C1414JV18 follow. [1] (continued)
A
B
C
www.DataSheet4UD.com
E
F
G
H
J
K
L
M
N
P
R
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1412JV18 (2M x 18)
345678
A
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
BWS1
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
K
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
NC/288M
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
AAACAA
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1414JV18 (1M x 36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ NC/288M NC/72M WPS BWS2
K
BWS1
RPS
A NC/144M CQ
B
Q27 Q18 D18
A BWS3 K BWS0 A
D17 Q17
Q8
C D27 Q28 D19 VSS A
A
A
VSS D16
Q7
D8
D
D28 D20 Q19 VSS VSS VSS VSS
VSS Q16 D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS VDDQ Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS VDDQ D11
Q11
Q2
M
D33 Q34 D25 VSS VSS VSS VSS
VSS D10
Q1
D2
N D34 D26 Q25 VSS A
A
A
VSS Q10
D9
D1
P Q35 D35 Q26 A A C A A Q9 D0 Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document #: 001-12561 Rev. *D
Page 5 of 26
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5 Page CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Write Cycle Descriptions
The write cycle description table for CY7C1425JV18 follows. [2, 8]
BWS0
L
L
H
K
L–H
–
L–H
K Comments
– During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
– No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
www.DataShWeetr4iUte.coCmycle Descriptions
The write cycle description table for CY7C1414JV18 follows. [2, 8]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Document #: 001-12561 Rev. *D
Page 11 of 26
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11 Page |
Páginas | Total 26 Páginas | |
PDF Descargar | [ Datasheet CY7C1412JV18.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY7C1412JV18 | (CY7C14xxJV18) SRAM 2-Word Burst Architecture | Cypress Semiconductor |
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