PDF CY7C1410V18 Data sheet ( Hoja de datos )

Número de pieza	CY7C1410V18
Descripción	(CY7C14xxV18) SRAM 2-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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PRELIMINARY CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 200-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and www.DataSheet4UW.croimte ports (data transferred at 400 MHz) @ 200 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x8, x9, x18, and x36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD • 15 × 17 × 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix) • Variable drive HSTL output buffers • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1410V18 – 4M x 8 CY7C1425V18 – 4M x 9 CY7C1412V18 – 2M x 18 CY7C1414V18 – 1M x 36 The CY7C1410V18, CY7C1425V18, CY7C1412V18, and CY7C1414V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1410V18) or 9-bit words (CY7C1425V18) or 18-bit words (CY7C1412V18) or 36-bit words (CY7C1414V18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05592 Rev. Revised June 07, 2004 1 page PRELIMINARY Pin Configurations (continued) A B C D E F G www.DataSheet4U.cHom J K L M N P R 1 CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK CY7C1412V18 (2M × 18) – 15 × 17 FBGA 34 56 78 A D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A K NC/288M RPS K BWS0 A A A VSS VSS VSS VSS VSS VSS VDDQ VSS VDD VDDQ VSS VDD VDDQ VSS VDD VDDQ VSS VDD VDDQ VSS VDD VDDQ VSS VSS VDDQ VSS VSS VSS A A VSS CAA CAA CY7C1414V18 (1M × 36) – 15 × 17 FBGA 12 3 4 5 6 78 A CQ NC/288M NC/72M WPS BWS2 K BWS1 RPS B Q27 Q18 D18 A BWS3 K BWS0 A C D27 Q28 D19 VSS A A A VSS D D28 D20 Q19 VSS VSS VSS VSS VSS E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ M D33 Q34 D25 VSS VSS VSS VSS VSS N D34 D26 Q25 VSS A A A VSS P Q35 D35 Q26 A ACAA R TDO TCK A A A CAA CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI 9 A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Document #: 38-05592 Rev. Page 5 of 23 5 Page PRELIMINARY CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................... –10°C to +85°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V DC Voltage Applied to Outputs in High-Z State .................................... –0.5V to VDDQ + 0.3V DC Input Voltage[12] ............................ –0.5V to VDDQ + 0.3V Ambient Range Temperature (TA) Com’l 0°C to +70°C VDD[13] 1.8 ± 0.1 V VDDQ[13] 1.4V to VDD Electrical Characteristics Over the Operating Range[9, 13] www.DataSheet4DUC.cEomlectrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Power Supply Voltage 1.7 1.8 I/O Supply Voltage 1.4 1.5 Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[12] Input LOW Voltage[12] [10] [11] IOH = −0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 Input Load Current GND ≤ VI ≤ VDDQ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled Input Reference Voltage[14] Typical Value = 0.75V −5 −5 0.68 0.75 VDD Operating Supply VDD = Max., IOUT = 0 167 MHz mA, f = fMAX = 1/tCYC 200 MHz 250 MHz ISB1 Automatic Power-down Max. VDD, Both Ports Current Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static Shaded areas contain advance information. Please contact your local Cypress Sales representative for availability of these parts. 167 MHz 200 MHz 250 MHz Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ+0.3 VREF – 0.1 5 5 0.95 TBD TBD TBD TBD TBD TBD Unit V V V V V V V V µA µA V mA mA mA mA mA mA AC Input Requirements Over the Operating Range Parameter Description Test Conditions Min. Typ. VIH Input High (Logic 1) Voltage VREF + 0.2 – VIL Input Low (Logic 0) Voltage –– Notes: 9. All voltage referenced to Ground. 10. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs. 11. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 12. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 13. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 14. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller. Max. – VREF - 0.2 Unit V V Document #: 38-05592 Rev. ** Page 11 of 23 11 Page

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