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DD-03296 Schematic ( PDF Datasheet ) - DDC

Teilenummer DD-03296
Beschreibung 96-Channel Discrete to Digital Interface
Hersteller DDC
Logo DDC Logo 




Gesamt 18 Seiten
DD-03296 Datasheet, Funktion
DD-03296
96-CHANNEL DISCRETE-TO-DIGITAL
INTERFACE
DESCRIPTION
APPLICATIONS
The DD-03296 device is a 96-channel
discrete-to-digital interface with uni-
versal HlRF-isolated inputs that
www.DataSheaect4cUep.cto2m8 V/Open, Open/Gnd and 28
V/Gnd signals.
The output is an addressable 8- or
16-bit tri-state port, selectable for
channel data, status, bounce, built-in
self-test (BIST) and major fault, and is
compatible with TTL logic.
The DD-03296 is specifically
designed to address built-in self-test
autonomy, fault isolation and toler-
ance.
Because of its high reliability and low
cost, these features enable the DD-
03296 to satisfy a variety of interface
requirements in aerospace applica-
tions, including flight critical, essen-
tial, and nonessential functions.
FEATURES
HIRF Layer
Universal Inputs
28 V/Gnd
Open/Gnd
28 V/Open
Built-in Self-Test
Soft Failure Reporting
Higher MTBUR
ARINC 429 Output Port
REFERENCE
INPUT
REFERENCE INPUT
DATA
BOUNCE
96
96
DISCRETE
INPUTS
PROCESSOR AND
TEST MATRIX
BIT
FAULT
96
96
96
SHIFT H/L TEST
MATRIX
ENABLE HI
5
TRANSFER DISCRETE ENABLE LO
5
33
ADDRESS DISCRETE DATA EN
DECODER ARINC DATA EN
SEL0
SEL1
SEL2
1 MHZ
RESET*
DUAL REDUNDANT
CLOCK AND
CONTROL LOGIC
ENABLE*
ADDRESS (A5..A0)
8/16 BUS
ARINC 429 DATA RATE
ARINC 429 MESSAGE RATE
DISCRETE
TRI-STATE
DRIVERS
16
DATA BUS
DATA (8/16 BITS)
DISCRETE
DATA
TRANSFER
VERIFIER
ARINC
DATA
TRANSFER
VERIFIER
TRANSFER FAULT
96 FAULT
96 BIT
TRANSFER FAULT
FAULT
PROCESSING
CIRCUITRY
DISCRETE
FAULT
ARINC
FAULT
FAULT*
ARINC 429
TRI-STATE
DRIVERS
16 DATA BUS
TRI-STATE ENABLES
READY
10µS CLOCK
80µS CLOCK
ARINC 429
XMITTER
(TTL)
2 ARINC 429
OUTPUT
NOTE: (*) Indicates active low.
© 1993, 1999 Data Device Corporation
U.S. Patent No. 5526288
FIGURE 1. DD-03296 BLOCK DIAGRAM
DATA READY






DD-03296 Datasheet, Funktion
TABLE 3. WORD MODE (16-BIT BUS)
ADDRESS (A5 . . A0)
DATA (D15..D0)
00 000X
BOUNCE CH_16 CH_01
00 001X
BOUNCE CH_32 CH_17
00 010X
BOUNCE CH_48 CH_33
00 011X
BOUNCE CH_64 CH_49
00 100X
BOUNCE CH_80 CH_65
00 101X
BOUNCE CH_96 CH_81
00 110X
FAULT CH_16..CH_01
00 111X
FAULT CH_32..CH_17
01 000X
FAULT CH_48..CH_33
01 001X
FAULT CH_64..CH_49
www.DataSheet40U1.c0o1m0X
01 011X
TEST PATTERN 0’s and 1’s
FAULT CH_80..CH_65
01 100X
FAULT CH_96..CH_81
01 101X
DATA CH_16..CH_01
01 110X
DATA CH_32..CH_17
01 111X
DATA CH_48..CH_33
10 000X
DATA CH_64..CH_49
10 001X
DATA CH_80..CH_65
10 010X
DATA CH_96..CH_81
10 011X
NOT USED
10 100X
STATUS REGISTER
10 101X
TEST PATTERN 1’s and 0‘s
10 110X
FACTORY TEST WORD 1
10 111X
FACTORY TEST WORD 2
11 000X
FACTORY TEST WORD 3
11 001X
FACTORY TEST WORD 4
11 010X
NOT USED
11 011X
:
11 111X
NOT USED
NOTES FOR TABLES 3 AND 4.
Note 1: A true BOUNCE bit indicates that the input signal of the associat-
ed channel changed in an alternating fashion, i.e., OFF-ON-OFF or ON-
OFF-ON in three successive samples at the selected sampled rate.
Note 2: A FAULT bit that is true indicates that the associated channel
has a major problem and that the associated data should not be
believed. A FAULT indication is a HARD FAULT condition indicating
that the Built-In-Test has failed.
Note 3: A DATA bit indicates the input discrete state for the associat-
ed channel over the last two data samples taken.
Note 4: The two available TEST PATTERNS contain an alternating
string of 1’s and 0’s, and 0’s and 1’s, which can be used to verify that
all of the data bits are operational (i.e., there are no stuck bits). The two
test patterns have been located at addresses of alternating address bits
so that the address decoder bits are tested at the same time.
TABLE 4. BYTE MODE (8-BIT BUS)
ADDRESS (A5. . A0)
00 0000
00 0001
DATA (D7..D0)
BOUNCE CH_08 CH_01
BOUNCE CH_16 CH_09
00 0010
00 0011
00 0100
BOUNCE CH_24 CH_17
BOUNCE CH_32 CH_25
BOUNCE CH_40 CH_33
00 0101
00 0110
BOUNCE CH_48 CH_41
BOUNCE CH_56 CH_49
00 0111
00 1000
00 1001
BOUNCE CH_64 CH_57
BOUNCE CH_73 CH_65
BOUNCE CH_80 CH_74
00 1010
00 1011
BOUNCE CH_88 CH_81
BOUNCE CH_96 CH_89
00 1100
00 1101
00 1110
FAULT CH_08 CH_01
FAULT CH_16 CH_09
FAULT CH_24 CH_17
00 1111
01 0000
01 0001
FAULT CH_32 CH_25
FAULT CH_40 CH_33
FAULT CH_48 CH_41
01 0010
01 0011
FAULT CH_56 CH_49
FAULT CH_64 CH_57
01 0100
01 0101
01 0110
TEST PATTERN 0’s and 1‘s
TEST PATTERN 0’s and 1‘s
FAULT CH_73 CH_65
01 0111
01 1000
01 1001
01 1010
01 1011
FAULT CH_80 CH_74
FAULT CH_88 CH_81
FAULT CH_96 CH_89
DATA CH_08..CH_01
DATA CH_16..CH_09
01 1100
01 1101
01 1110
DATA CH_24..CH_17
DATA CH_32..CH_25
DATA CH_40..CH_33
01 1111
10 0000
DATA CH_48..CH_41
DATA CH_56..CH_49
10 0001
10 0010
10 0011
DATA CH_64..CH_57
DATA CH_72..CH_65
DATA CH_80..CH_73
10 0100
10 0101
10 0110
DATA CH_88..CH_81
DATA CH_96..CH_89
NOT USED
10 0111
10 1000
NOT USED
STATUS REGISTER LO
10 1001
10 1010
10 1011
STATUS REGISTER HI
TEST PATTERN 1’s and 0’s
TEST PATTERN 1’s and 0’s
10 1100
10 1101
TEST WORD 1 LO
TEST WORD 1 HI
10 1110
10 1111
11 0000
TEST WORD 2 LO
TEST WORD 2 HI
TEST WORD 3 LO
11 0001
11 0010
TEST WORD 3 HI
TEST WORD 4 LO
11 0011
11 0100
11 0111
TEST WORD 4 HI
NOT USED
:
11 1111
NOT USED
6

6 Page









DD-03296 pdf, datenblatt
TOP VIEW
N/C
SYNC
DATA(A)
CA
www.DataSheet4U.com
A OUT
-V
1
2
3
4
5
6
7
14 V 1
13 CLOCK
12 DATA(B)
11 C B
10 B OUT
9 +V
8 GND
TOP VIEW
N/C
SYNC
DATA(A)
CA
A OUT
-V
GND
1
2
3
4
5
6
7
8
16 V 1
15 N/C
14 CLOCK
13 DATA(B)
12 C B
11 B OUT
10 N/C
9 +V
FIGURE 8. DD-03182VP PIN CONFIGURATION
FIGURE 9. DD-03182DC AND GP PIN CONFIGURATION
TOP VIEW
S
YG
NN
CD
43
N
/
V
R
E
V
NN
//
CF
1 CC
2 1 28 27 26
N/C 5
DATA (A) 6
N/C 7
N/C 8
CA 9
DD-03182PP
PLCC
N/C 10
N/C 11
12 13 14
N A -v
/O
CU
T
15 16 17 18
G +v B N
N O/
D UC
T
25 CLOCK
24 N/C
23 DATA (B)
22 CB
21 N/C
20 N/C
19 N/C
FIGURE 10. DD-03182PP PIN CONFIGURATION
12

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