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PDF SSD1821 Data sheet ( Hoja de datos )
| Número de pieza | SSD1821 | |
| Descripción | (SSD1820A / SSD1821) LCD Segment / Common Driver | |
| Fabricantes | Solomon Systech | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SSD1821 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
Advance Information
LCD Segment / Common Driver
with Controller
CMOS
SSD1820A/21 is a single-chip CMOS LCD driver with controller for a liquid crystal
dot-matrix graphic display system. SSD1820A consists of 194 high voltage driving out-
www.DataSheet4Up.uctompins for driving 128 Segments, 64 Commons and 2 icon driving Commons, while
SSD1821 consists of 210 high voltage driving output pins for driving 128 Segments,
80 Commons and 2 icon driving Commons.
SSD1820A
SSD1821
TAB
SSD1820A/21 displays data directly from its internal 128x65/128X81 bits Graphic
Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through
a hardware selectable 6800-/8080-series compatible Parallel Interface or 3/4 wires
Serial Peripheral Interface.
SSD1820A/21 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-
Chip Bias Divider and an On-Chip Oscillator which reduce the number of external
components. With the special design on minimizing power consumption and die/pack-
age layout, SSD1820A/21 is suitable for any portable battery-driven applications re-
quiring a long operation period and a compact size.
• 128 x 64/80 Graphic Display with a Icon Line
• Programmable Multiplex ratio [16Mux - 65Mux/81Mux] (Partial Display)
• Single Supply Operation, 1.8 V - 3.3V
• Low Current Sleep Mode(<1.0uA)
• On-Chip Voltage Generator / External Power Supply
• Software selectable 2X / 3X / 4X / 5X / 6X On-Chip DC-DC Converter
• On-Chip Oscillator
• Software Selectable On-Chip Bias Dividers
• Programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio
• Maximum +15.0V LCD Driving Output Voltage
• Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Par-
allel Interface, 3-wire Serial Peripheral Interface or 4-wire Serial Peripheral Interface
• On-Chip 128 x 65/81 Graphic Display Data RAM
• Re-mapping of Row and Column Drivers
• Vertical Scrolling
• Display Offset Control
• 64 Levels Internal Contrast Control
• External Contrast Control
• Maximum 17MHz SPI or 15MHz PPI operation
• Selectable LCD Driving Voltage Temperature Coefficients (2 settings)
• Available in Gold Bump Die and Standard TAB (Tape Automated Bonding) Package
Gold Bump Die
ORDERING INFORMATION
SSD1820AZ
SSD1821Z
SSD1820ATR1
SSD1821TR1
Gold Bump Die
Gold Bump Die
TAB
TAB
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Copyright © 2002/2003 Solomon Systech Limited.
REV 1.4
01/03
1 page  
www.DataSheet4U.com
SOLOMON
COM5
COM4
COM3
COM2
COM1
COM0
ICONS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
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SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
COM32
COM33
COM34
COM35
COM36
COM37
COM38
144
285
115
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1
N/C
N/C
:
N/C
CL
VSS
VR
VR
VL6
VL6
VL6
VL5
VL5
VL5
VL4
VL4
VL4
VL3
VL3
VL3
VL2
VL2
VL2
VSS
INTRS
VDD
VEXT
REF
VSS
C4P
C4P
C4P
C2N
C2N
C2N
C2N
C2P
C2P
C2P
C1P
C1P
C1P
C1N
C1N
C1N
C1N
C3P
C3P
C3P
N/C
N/C
N/C
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCI
VCI
VCI
VCI
VCI
VDD
VDD
VDD
D7 (SDA)
D7 (SDA)
D6 (SCK)
D6 (SCK)
D5
D4
D3
D2
D1
D0
VDD
E(/RD)
E(/RD)
R/W(/WR)
R/W(/WR)
VSS
D/C
D/C
D/C
/RES
VDD
/CS
/CS
VSS
PS1
VDD
VSS
PS0
VDD
N/C
N/C
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N/C
N/C
Note:
1. Diagram showing the face of the die.
2. Coordinates are reference to center of the chip.
3. Unit of coordinates and Size of all alignment
marks are in um.
4. All alignment keys do not contain gold bump.
Pin#1
SSD1820AZ Die Pin Assignment
DRAWING NOT TO SCALE
Die Size: 10.8mm x 1.96mm
Die Thickness: 534um +/- 25um
Bump Height: 18um +/- 3um
REV 1.4 SSD1820A/21
01/03
5
5 Page 
VL5, VL4, VL3 and VL2
LCD driving voltages. They can be supplied externally or gener-
ated by the internal bias divider. They have the following relation-
ship:
VL6 > VL5 > VL4 > VL3 > VL2 > VSS
1:a bias
VL5 (a-1)/a*VL6
VL4 (a-2)/a*VL6
VL3 2/a*VL6
www.DaVtaL2Sheet4U.co1m/a*VL6
For SSD1820A, a equals to 9 at POR.
For SSD1821, a equal to 10 at POR.
COM0 - COM63/COM79
These pins provide the row driving signal COM0 - COM63/
COM79 to the LCD panel. See Table 1 or 2 about the COM signal
mapping in different multiplex ratio N.
ICONS
This pin is the special icons line COM signal output.
SEG0 - SEG127
These pins provide the LCD column driving signal. Their voltage
level is VSS during sleep mode and standby mode.
CL
This pin is the external clock input for the device which is
enabled by using an extended command. Under normal operation,
this pin should be left opened and internal oscillator will be used
after power on reset.
N/C
These No Connection pins should NOT be connected to any sig-
nal pins nor shorted together. They should be left open.
SOLOMON
REV 1.4 SSD1820A/21
01/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SSD1821.PDF ] | |
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