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Teilenummer | E5108ASE |
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Beschreibung | EDE5108ASE | |
Hersteller | Elpida Memory | |
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Gesamt 30 Seiten PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AGSE (128M words × 4 bits)
EDE5108AGSE (64M words × 8 bits)
Description
The EDE5104AGSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108AGSE is a 512M bits DDR2 SDRAM
www.DataSheet4Uo.crogmanized as 16,777,216 words × 8 bits × 4 banks.
They are packaged in 60-ball FBGA (µBGA) package.
Features
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• SSTL_18 compatible I/O
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
• FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0715E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
EDE5104AGSE, EDE5108AGSE
Recommended DC Operating Conditions (SSTL_18)
Parameter
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD
1.7
1.8 1.9
V4
Supply voltage for output
VDDQ
1.7
1.8 1.9
V4
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
Termination voltage
VTT
VREF − 0.04
VREF
VREF + 0.04
V
3
DC input logic high
VIH (DC)
VREF + 0.125
VDDQ + 0.3
V
DC input low
AC input logic high
-6C, -6E
-5C, -4A
www.DataSheet4UA.cCominput low
-6C, -6E
-5C, -4A
VIL (DC)
VIH (AC)
VIH (AC)
VIL (AC)
VIL (AC)
−0.3
VREF + 0.200
VREF + 0.250
VREF – 0.125
VREF − 0.200
VREF − 0.250
V
V
V
V
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and
VDDL tied together.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
6
6 Page EDE5104AGSE, EDE5108AGSE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
-6C, -6E
-5C
-4A
Frequency (Mbps)
667 533 400
Parameter
Symbol min.
max.
min.
max.
min.
max.
Unit Notes
/CAS latency
Active to read or write command
delay
CL
tRCD
4 (-6C)
5 (-6E)
12 (-6C)
15 (-6E)
Precharge command period
tRP
12 (-6C)
15(-6E)
Active to active/auto refresh
command time
tRC
57 (-6C)
60 (-6E)
DQ output access time from CK, /CK tAC
−450
www.DataSheet4UD.cQomS output access time from CK,
/CK
tDQSCK −400
CK high-level width
tCH 0.45
5
+450
+400
0.55
4
15
15
60
−500
−450
0.45
5
+500
+450
0.55
3
15
15
55
−600
−500
0.45
5
+600
+500
0.55
tCK
ns
ns
ns
ps
ps
tCK
CK low-level width
CK half period
Clock cycle time
tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tHP
min.
(tCL, tCH)
min.
(tCL, tCH)
min.
(tCL, tCH)
ps
tCK 3000 8000 3750 8000 5000 8000 ps
DQ and DM input hold time
tDH 175
225
275
ps 5
DQ and DM input setup time
Control and Address input pulse
width for each input
DQ and DM input pulse width for
each input
Data-out high-impedance time from
CK,/CK
Data-out low-impedance time from
CK,/CK
DQS-DQ skew for DQS and
associated DQ signals
DQ hold skew factor
tDS
tIPW
tDIPW
tHZ
tLZ
tDQSQ
tQHS
DQ/DQS output hold time from DQS tQH
Write command to first DQS latching
transition
tDQSS
DQS input high pulse width
tDQSH
100
0.6
100
0.6
150
0.6
ps 4
tCK
0.35
0.35
0.35
tCK
tAC max. tAC max. tAC max. ps
tAC min. tAC max. tAC min. tAC max. tAC min. tAC max. ps
240 300 350 ps
tHP –
tQHS
340
tHP –
tQHS
400
tHP –
tQHS
450
ps
ps
WL − 0.25 WL + 0.25 WL − 0.25 WL + 0.25 WL − 0.25 WL + 0.25 tCK
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL 0.35
0.35
0.35
tCK
DQS falling edge to CK setup time tDSS 0.2
0.2
0.2
tCK
DQS falling edge hold time from CK tDSH 0.2
0.2
0.2
tCK
Mode register set command cycle
time
tMRD
2
2
2
tCK
Write postamble
tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Write preamble
tWPRE 0.35
0.35
0.35
tCK
Address and control input hold time tIH 275
375
475
ps 5
Address and control input setup time tIS 200
250
350
ps 4
Read preamble
tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read postamble
tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Active to precharge command
tRAS 45
70000 45
70000 40
70000 ns
Active to auto-precharge delay
tRAP tRCD min.
tRCD min.
tRCD min.
ns
Preliminary Data Sheet E0715E20 (Ver. 2.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ E5108ASE Schematic.PDF ] |
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