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W65C02S Schematic ( PDF Datasheet ) - WDC

Teilenummer W65C02S
Beschreibung Microprocessor
Hersteller WDC
Logo WDC Logo 




Gesamt 30 Seiten
W65C02S Datasheet, Funktion
The Western Design Center, Inc.
February 2004
W65C02S Data Sheet
www.DataSheet4U.com
W65C02S
Microprocessor
DATA SHEET
© The Western Design Center, Inc., 2003. All rights reserved
WDC






W65C02S Datasheet, Funktion
The Western Design Center, Inc.
W65C02S Data Sheet
2 FUNCTIONAL DESCRIPTION
The internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) Control Section.
Instructions obtained from program memory are executed by implementing a series of data transfers within the
Register Section. Signals that cause data transfers are generated within the Control Section.
2.1 Instruction Register (IR) and Decode
www.DataSTheheet4OU.pceormation Code (OpCode) portion of the instruction is loaded into the Instruction Register from the Data Bus
and is latched during the OpCode fetch cycle. The OpCode is then decoded, along with timing and interrupt signals,
to generate various control signals for program execution.
2.2 Timing Control Unit (TCU)
The Timing Control Unit (TCU) provides timing for each instruction cycle that is executed. The TCU is set to zero for each
instruction fetch, and is advanced at the beginning of each cycle for as many cycles as is required to complete the instruction.
Data transfers between registers depend upon decoding the contents of both the IR and the TCU.
2.3 Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place within the ALU. In addition to data operations, the ALU also
calculates the effective address for relative and indexed addressing modes. The result of a data operation is stored in
either memory or an internal register. Carry, Negative, Overflow and Zero flags are updated following the ALU data
operation.
2.4 Accumulator Register (A)
The Accumulator Register (A) is an 8-bit general purpose register which holds one of the operands and the result of
arithmetic and logical operations. Reconfigured versions of this processor family could have additional
accumulators.
2.5 Index Registers (X and Y)
There are two 8-bit Index Registers (X and Y) which may be used as general purpose registers or to provide an index
value for calculation of the effective address. When executing an instruction with indexed addressing, the
microprocessor fetches the OpCode and the base address, and then modifies the address by adding the Index
Register contents to the address prior to performing the desired operation.
2.6 Processor Status Register (P)
The 8-bit Processor Status Register (P) contains status flags and mode select bits. The Carry (C), Negative (N),
Overflow (V) and Zero (Z) status flags serve to report the status of ALU operations. These status flags are tested
with Conditional Branch instructions. The Decimal (D) and IRQB disable (I) are used as mode select flags. These
flags are set by the program to change microprocessor operations. Bit 5 is available for a user status or mode bit.
2.7 Program Counter Register (PC)
The Western Design Center, Inc.
W65C02S Data Sheet
6

6 Page









W65C02S pdf, datenblatt
The Western Design Center, Inc.
W65C02S Data Sheet
FFFE, F
FFFC, D
FFFA, B
Table 3-1 Vector Locations
BRK/IRQB
RESB
NMIB
Software/Hardware
Hardware
Hardware
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Table 3-2 Pin Function Table
Pin
A0-A15
BE
D0-D7
IRQB
MLB
NC
NMIB
PHI1O
PHI2
PHI2O
RDY
RESB
RWB
SOB
SYNC
VDD
VPB
VSS
Description
Address Bus
Bus Enable
Data Bus
Interrupt Request
Memory Lock
No Connection
Non-Maskable Interrupt
Phase 1 Out Clock
Phase 2 In Clock
Phase 2 Out Clock
Ready
Reset
Read/Write
Set Overflow
Synchronize
Positive Power Supply
Vector Pull
Internal Logic Ground
The Western Design Center, Inc.
W65C02S Data Sheet
12

12 Page





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