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PDF ASM5I961P Data sheet ( Hoja de datos )
| Número de pieza | ASM5I961P | |
| Descripción | Low Voltage Zero Delay Buffer | |
| Fabricantes | Alliance Semiconductor | |
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July 2005
ASM5I961P
rev 0.2
Low Voltage Zero Delay Buffer
Features
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
www.DataSheet4U.com LVPECL Reference Clock Options
LQFP Packaging
±50pS Cycle–Cycle Jitter
150pS Output Skews
Functional Description
The ASM5I961P is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
The ASM5I961P is offered with two different input
configurations. The ASM5I961P offers an LVCMOS
reference clock while the ASM5I961P offers an LVPECL
reference clock.
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The ASM5I961P is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50Ω transmission lines. For series
terminated lines the ASM5I961P can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP package to provide
the optimum combination of board density and
performance.
Block Diagram
PCLK
PCLK
FB_IN
F_RANGE
OE
VCC
50K
50K 50K
Ref PLL
100-200 MHz
50-100 MHz
FB
50K
0
1
50K
50K
Q0
Q1
Q2
Q3
Q14
Q15
Q16
QFB
Figure 1. ASM5I961P Logic Diagram
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
July 2005
rev 0.2
Table 7: AC Characteristics (VCC = 2.5V ± 5%, TA = -40°C to +85°C)1
Symbol
Characteristic
fref
Input Frequency
F_RANGE = 0
F_RANGE = 1
fmax
Maximum Output
Frequency
F_RANGE = 0
F_RANGE = 1
frefDC
t(φ)
www.DataSheet4tUsk.(cOo) m
DCO
Reference Input Duty Cycle
Propagation Delay2
PECL_CLK to
(static phase offset)
FB_IN
Output–to–Output Skew3
Output Duty Cycle
F_RANGE = 0
F_RANGE = 1
tr, tf
tPLZ,HZ
tPZL,LZ
tJIT(CC)
tJIT(PER)
tJIT(φ)
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
I/O Phase Jitter
RMS (1σ)4
RMS (1σ)
RMS (1σ)
F_RANGE = 0
F_RANGE = 1
tlock Maximum PLL Lock Time
Notes:
1. AC characteristics apply for parallel output termination of 50Ω to VTT.
2. tPD applies for VCMR = VCC–1.3V and VPP = 800mV
3. See applications section for part–to–part skew calculation
4. See applications section for calculation for other confidence factors than 1σ
Min
100
50
100
50
25
–50
40
45
0.1
ASM5I961P
Typ
90
50
50
7.0
Max
200
100
200
100
75
175
150
60
55
1.0
10
10
15
10
0.0015 ⋅ T
0.0010 ⋅ T
10
Unit
MHz
MHz
%
pS
pS
%
nS
nS
nS
pS
pS
nS
mS
Condition
PLL locked
0.6 to 1.8V
T = Clock
Signal
Period
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 14
5 Page 
July 2005
rev 0.2
PCLK
PCLK
VPP
VCMR
Ext_FB
t(Ø)
VCC
VCC ÷2
GND
Figure 12. Propagation Delay (t(Ø)). Static phase offset
test reference
www.DataSheet4U.com
VCC
VCC ÷2
GND
tP
T0
DC= (tP ÷T0 Χ 100%)
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
Figure 14. Output Duty Cycle (DC)
ASM5I961P
VCC = 3.3V VCC = 2.5V
2.4 1.8V
0.55 0.6V
tF tR
Figure 13. Output Transition Time Test Reference
VCC
VCC ÷2
GND
tSK(O)
VCC
VCC ÷2
GND
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 15. Output–to–Output Skew tSK(O)
TN TN-1
TJIT(CC) =│TN-TN-1 mean│
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs
Figure 16. Cycle-to-cycle Jitter
PCLK
PCLK
T0 TJIT(PER) =│TN-1/f0│
The deviation in cycle time of a signal with respect to the
ideal period over a random sample of cycles
Figure 17. Period Jitter
Ext_FB
TJIT(Ø) =│T0-T1 mean│
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
Figure 18.I/O Jitter
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 14
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| PDF Descargar | [ Datasheet ASM5I961P.PDF ] | |
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