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PDF ASM5I2309A Data sheet ( Hoja de datos )
| Número de pieza | ASM5I2309A | |
| Descripción | (ASM5I2305A / ASM5I2309A) 3.3 V Zero Delay Buffer | |
| Fabricantes | Alliance Semiconductor | |
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September 2005
ASM5P2309A
ASM5P2305A
rev 1.6
3.3V Zero Delay Buffer
General Features
15MHz to 133MHz operating range, compatible
with CPU and PCI bus frequencies.
Zero input - output propagation delay.
Multiple low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
www.DataSheet4U.com One input drives 9 outputs, grouped as
4 + 4 + 1(ASM5P2309A).
One input drives 5 outputs (ASM5P2305A).
Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium® based systems.
Test Mode to bypass PLL (ASM5P2309A only,
Refer Select Input Decoding Table).
Available in 16pin 150-mil SOIC, 4.4 mm TSSOP
(ASM5P2309A), and in 8pin 150-mil SOIC
package (ASM5P2305A).
3.3V operation, advanced 0.35µ CMOS
technology.
Functional Description
ASM5P2309A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16-pin package. The ASM5P2305A is the
eight-pin version of the ASM5P2309A. It accepts one
reference input and drives out five low-skew clocks.
The -1H version of the ASM5P23XXA operates at up to
133MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P2309A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. The select input also
allows the input clock to be directly applied to the outputs
for chip and system testing purposes.
Multiple ASM5P2309A and ASM5P2305A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 350pS, and the output to output skew is
guaranteed to be less than 250pS.
The ASM5P2309A and the ASM5P2305A are available in
two different configurations, as shown in the ordering
information table. The ASM5P2305A-1/ ASM5P2309A-1 is
the base part. The ASM5P2305A-1H/ ASM5P2309A-1H is
the high drive version of the -1 and its rise and fall times
are much faster than -1 part.
Block Diagram
REF
PLL
ASM5P2305A
CLKOUT
REF
CLK1
CLK2
CLK3
CLK4
PLL MUX
S2 Select Input
Decoding
S1
ASM5P2309A
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
September 2005
ASM5P2309A
ASM5P2305A
rev 1.6
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
www.DataSheet4JUun.ccotmion Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Min Max Unit
-0.5 +7.0
V
-0.5 VDD + 0.5
-0.5 7
V
V
-65 +150 °C
260 °C
150 °C
2000
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can
affect device reliability.
Operating Conditions for ASM5P2305A and ASM5P2309A - Commercial Temperature Devices
Parameter
Description
VDD Supply Voltage
TA Operating Temperature (Ambient Temperature)
CL Load Capacitance, below 100MHz
CL Load Capacitance, from 100MHz to 133MHz
CIN Input Capacitance
Min Max
3.0 3.6
0 70
30
10
7
Unit
V
°C
pF
pF
pF
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 20
5 Page 
September 2005
rev 1.6
Test Circuits
ASM5P2309A
ASM5P2305A
0.1uF
www.DataSheet4U.com
0.1uF
TEST CIRCUIT # 1
VDD
OUTPUTS
VDD
CLKOUT
CLOAD
GND GND
0.1uF
0.1uF
TEST CIRCUIT # 2
VDD
OUTPUTS
VDD
GND GND
1KΩ
1KΩ
10pF
For parameter t8 (output skew rate) on -1H devices
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 20
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| PDF Descargar | [ Datasheet ASM5I2309A.PDF ] | |
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