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PDF MSM7654 Data sheet ( Hoja de datos )
| Número de pieza | MSM7654 | |
| Descripción | NTSC/PAL Digital Video Encoder | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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E2F0023-29-83
¡¡SemicondSucetormiconductor
MSM7654
NTSC/PAL Digital Video Encoder
This version: AMugS.M19796954
Previous version: Dec. 1998
GENERAL DESCRIPTION
The MSM7654, which is a digital video encoder supporting NTSC/PAL formats, converts digital
image data to an analog video signal.
The encoder can receive the digital image or RGB digital image signals conforming to ITU-R
BT.601 as an input signal.
The encoder can output simultaneously the composite video and S-video signals, and it can also
www.DataSheoetu4Utp.cuotmthe RGB analog signal by switching.
The encoder can control luminance (Y) signal output levels of the composite video and S-video
signals.
FEATURES
• Video signal system: NTSC/PAL
• Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines)
• Input digital level: conforms to ITU-R BT.601 (CCIR601)
• Input-output timing: conforms to ITU-R BT.656 or ITU-R BT.624-4
• Input signal sampling ratio : Y:Cb:Cr = 4:2:2 or 4:1:1/R:G:B = 8:8:8
• Supported input interface
· ITU-R BT.656
· YCbCr format (8-bit input)
· ITU-R BT.601 (8-bit (Y) + 8-bit (CbCr) input)
· RGB (24-bit input)
• Pixel frequency (Sampling frequency) :
· 12.272727 MHz (24.545454 MHz) : NTSC Square Pixel
· 13.5 MHz (27 MHz) : NTSC/PAL ITU-R BT.601
· 14.318182 MHz (28.636364 MHz) : NTSC 4Fsc
· 14.75 MHz (29.5 MHz) : PAL Square Pixel
• Output format
· Selectable composite & S-video or RGB
· 37.5 W driving capability
• Master or slave operation (slave operation only in ITU-R BT.656 mode)
• Internal 3ch 10-bit DAC
• 3-bit title/graphics can be displayed (only for composite and S-video signals)
• Color bar function
• I2C-bus host interface function
• Brightness level adjust of 100% to 68.75% (only for composite and S-video signals)
• GENLOCK control
• 3.3 V single power supply (each I/O pin is 5 V tolerable)
• Package
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7654GA)
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¡ Semiconductor
MSM7654
PIN DESCRIPTIONS
Pin
1
2
3
4
5 to 8
www.DataSheet4U.com
9
10
11
12
13
14
15
16
17 to 24
25 to 32
33
34
35 to 42
43
44
45
46
I/O Symbol
Description
DVDD
3.3 V digital power supply.
I/O SDA I2C interface data bus.
I SCL I2C interface clock bus.
I RGBMODE Input signal select pin. "0" : YCbCr / "1" : RGB, Internal pull-down.
I MODE[3:0] Operation mode select pin. However, sleep mode is valid while RGBMODE
is "0". Internal pull-down.
0000 : NTSC ITU-R BT.656
0001 : NTSC 27 MHz YCbCr
0010 : NTSC 24.52 MHz Square Pixel
0011 : NTSC 28.64 MHz 4Fsc
0101 : NTSC 13.5 MHz YCbCr
0110 : NTSC 12.27 MHz
0111 : NTSC 14.32 MHz
1000 : PAL ITU-R BT.656
1001 : PAL 27 MHz YcbCr
1010 : PAL 29.5 MHz Square Pixel
1101 : PAL 13.5 MHz
1110 : PAL 14.75 MHz
1111 : Sleep Mode (Valid only
when RGBMODE is "0")
I MS Master/slave operation selection in other modes than ITU-R BT.656. Internal
pull-down. "1" : Master / "0" : Slave
Only slave mode is selected in ITU-R BT.656 mode (input of "1" is invalid)
I/O GENLOCK GENLOCK signal I/O pin.
O CSYNC_L Composite sync output pin.
I/O VSYNC_L Vertical sync input/output pin (output mode in master mode/input mode in
slave mode)
I/O HSYNC_L Horizontal signal input/output pin (output mode in master mode/input mode
in slave mode)
I BLANK_L Composite blank signal input pin.
DVDD 3.3 V digital power supply.
I DGND Digital GND.
I CD0 to CD7 8-bit digital image chrominance signal data input pins at pixel rate
operation. Level conforms to ITU-R BT.601. R signal input pins in RGB input
mode. CD7 is MSB. Fixed to "0" when not used.
I YD0 to YD7 8-bit digital image data input pins at double pixel rate operation. 8-bit digital
luminance signal data input pins at pixel rate operation. Level conforms to
ITU-R BT.601. G signal input pins in RGB input mode. YD7 is MSB.
DGND Digital GND
DVDD 3.3 V digital power supply
I BD0 to BD7 B signal input pins in RGB input mode. Fixed to "0" when not used.
O
FOUT
Field information output pin (Odd Field : "1", Even Field : "0") (Polarity can
be changed by the internal register.)
I RESET_L System reset pin.
I
TENB
Input pin for testing. Normally fixed to "0". Internal pull-down. The user
cannot use this pin.
I CLKX2 Clock input pin.
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5 Page 
¡ Semiconductor
MSM7654
3) I2C-bus Interface Input/Output Timing
When writing to internal registers, written contents are set to the internal registers MR1 [7] and
CR0 [2:1] during the vertical blanking period. On the other hand, written contents are
immediately set to the other internal registers.
(Note) Data cannot be changed when SCL is "H". Data line can be changed only when SCL is
"L".
The I2C-bus Interface Basic Input/Output Timing is shown below.
I2C-bus AC Characteristics
Parameter
www.DataSheeIt24CU-.bcuosmClock Cycle Time
I2C-bus High Level Cycle
I2C-bus Low Level Cycle
SDA-SCL Overlap Time
Symbol
tC_SCL
tH_SCL
tL_SCL
tOV
(Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)
Condition
Min. Typ. Max. Unit
Rpull_up = 4.7 kW 200 —
— ns
Rpull_up = 4.7 kW 100 —
— ns
Rpull_up = 4.7 kW 100 —
— ns
Rpull_up = 4.7 kW 40 — — ns
tOV
SDA MSB
SCL S 1
Start Condition
2
789
ACK
Data Line Stable: Data Valid Change of Data Allowed
tC_SCL
1
tL_SCL
2
3-8
tH_SCL
9
ACK
P
Stop Condition
I2C-bus Input/Output Basic Timing
4) Reset Input Timing
The reset timing is asynchronous with the clock timing.
Reset AC Characteristics
Parameter
Minimum Reset Pulse Width
Symbol
tW2
(Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)
Condition
Min. Typ. Max. Unit
—
81.5 —
— ns
CLKX2 (Input)
RESET-L (Input)
tW2
Reset Timing
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| Páginas | Total 53 Páginas | |
| PDF Descargar | [ Datasheet MSM7654.PDF ] | |
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