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PDF ZL10060 Data sheet ( Hoja de datos )
| Número de pieza | ZL10060 | |
| Descripción | MOPLL | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL10060
MOPLL with IF AGC Amplifier
Data Sheet
Features
• Highly integrated mixer/oscillator PLL and IF AGC
amplifier for multi band analog/digital terrestrial
tuners and/or cable tuners
• Low phase noise PLL frequency synthesizer
• AGC output level detect with digital controlled
TOP threshold
• >50 dB Desired/Undesired ratio without pre
www.DataSheet4Uf.iclotemring
• Separate analog and digital IF outputs
• >41 dB IF AGC Control range
• Power down modes to support power reduction
initiatives
• Four independent GPO
• 48 pin QFN Package
Applications
• DVB-T receiver systems
• ISDB-T receiver systems
• DVB-C cable receiver systems
• Terrestrial analog receivers
November 2005
Ordering Information
ZL10060LDG1 48 Pin QFN* Trays
ZL10060LDF1 48 Pin QFN* Tape and Reel
*Pb Free Matte Tin
-20°C to +85°C
Description
The ZL10060 is a 3 band MOPLL with IF AGC
amplifier. It down-converts the RF channel to a
standard IF followed by filtering and IF AGC
amplification for the digital channel. Each band
consists of a low noise preamplifier/mixer and local
oscillator with an external varactor tuned tank circuit.
An IF level detector is included for control of the RF
AGC. The Take Over Point and time constant are both
programmable.
The ZL10060 has high signal level handling
performance providing excellent performance in the
presence of high level unwanted signals.
All chip control is via I2C bus.
If higher performance is required, an alternative part,
ZL10063 is available with image reject down
conversion.
RF
Input
ZL10060
GPO
RF AGC
Tuning
VCO Tank
Circuits
Band
Pass
Filter
Analog Digital
IF SAW IF SAW
Analog
Analog IF Demod
PLL
AGC
Det
I2C
Control
Digital IF
Digital
Demod
IF AGC
I2C
Loop
Filter
Figure 1 - Basic Block Diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL10060
Data Sheet
www.DataSheet4U.com
IFAGC
SAB
SA
ADC
SDA
SCL
ADD
AGCOP
CNOPB
CNOP
CONT
VccRF
1
Vee
(PACKAGE
PADDLE)
ZL10060
IFIPB
IFIP
VccOSC
VeeOSC
LHIPB
LHOPB
LHOP
LHIP
LMOPB
LMOP
LLOPB
LLOP
Figure 2 - Pin Diagram
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Port Name
IFAGC
SAB
SA
ADC
SDA
SCL
ADD
AGCOP
CNOPB
CNOP
CONT
VccRF
SIPB
SIP
GPP0
GPP1
Function
IF amplifier AGC input
SAW filter driver output (analog)
SAW filter driver output (analog)
External ADC input
I2C bus serial data input/output
I2C bus serial clock input
I2C bus address selection input
AGC output
Analog converter output
Analog converter output
Paddle (Ground)
RF section supply
SAW filter driver input
SAW filter driver input
General purpose switching port
General purpose switching port
Table 1 - Pin Names
5
Zarlink Semiconductor Inc.
5 Page 
ZL10060
Data Sheet
which enables the use of more than one device in an I2C bus system. The address is selected by applying a voltage
to the ‘ADD’ input.
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are received. When the device is programmed into read
mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
2.0 Programming
The ZL10060 is fully programmable through the I2C interface. The device can also output data to the controller.
www.DataShee2t4.1U.comProgrammable Features
Feature
RF programmable
divider
Reference
programmable divider
Band selection
AGC Threshold
AGC Decay
Charge pump current
IF amplifier function
SAWF output select
Ports GPP[3:1]
PORT GPP0
VCO Trim
ADC input Select
Programmable power
Test modes
Programs PLL main divider
Description
Programs PLL reference divider to set required frequency step
Selects RF input and appropriate LO oscillator.
Sets the Input Power Level Threshold at which the AGC detector starts to generate a
control level.
Sets the AGC decay current.
Selects one of the four charge pump current settings.
The IF amplifier can be enabled independently of other circuit blocks.
Select the analog or digital SAW driver output.
These are configured as NPN buffers with 10 kohm pull-up resistors to Vcc.
Logic ‘1’ = on
Logic ‘0’ = off; default on power up
This is configured as a NPN open collector buffer. Logic ‘1’ = on
Logic ‘0’ = off; default on power up
Adjusts the VCO bias current to provide optimum phase noise performance.
Select either the internal AGC detect output level or the external level applied to the
ADC input pin.
The ZL10060 has various power saving modes.
Test modes to monitor and control internal PLL signals.
Table 2 - Programmable Features
2.2 Register Map
There are a total of 7 write registers, the first of which is the Address register. The control registers are described in
detail in the following section. The MSB of each register is written first.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
11
Zarlink Semiconductor Inc.
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