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PDF ZL10354 Data sheet ( Hoja de datos )

Número de pieza ZL10354
Descripción Diversity Enabled Nordig Unified DVB-T COFDM Terrestrial Demodulator
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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ZL10354
Diversity Enabled Nordig Unified DVB-T
COFDM Terrestrial Demodulator for
PC-TV and Hand-held Digital TV (DTV)
Data Sheet
Features
• Compliant with ETSI 300 744 DVB-T, Unified
Nordig and DTG performance specifications
• Diversity enabled multi-tuner solution.
• High performance with fast fully blind acquisition
and tracking capability
• Low power consumption: less than 0.32 W, and
eco-friendly standby and sleep modes
www.DataSheet4US.cionmgle 8 MHz SAW filter for 6, 7 & 8 MHz OFDM
• Superior single frequency network performance
• Fast AGC to track out signal fades
• Advanced Doppler tracking capability
• Enhanced frequency capture range to include
triple offsets
• External 4 MHz clock or single low-cost
20.48 MHz crystal, tolerance up to +/-200 ppm
• Automatic mode (2 K/8 K), guard and spectral
inversion detection
• Very low driver software overhead due to on-chip
state-machine control
• Novel RF level detect facility via a separate ADC
• Pre and post Viterbi-decoder bit error rates, and
uncorrectable block count
September 2005
Ordering Information
ZL10354QCG
ZL10354QCG1
ZL10354QCF
ZL10354QCF1
64 Pin LQFP
64 Pin LQFP*
64 Pin LQFP
64 Pin LQFP*
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Digital terrestrial set-top boxes
• Integrated digital televisions
• Personal video recorders
• PC-TV receivers
• Portable applications
Description
The ZL10354 is a superior fourth generation fully
compliant ETSI ETS300 744 COFDM demodulator that
exceeds, with margin, the performance requirements
of all known DVB-T digital terrestrial television
standards, including Unified Nordig and DTG.
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.

1 page




ZL10354 pdf
ZL10354
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5 - Outline Diversity System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - Outline of Dual Diversity/Play-and-Record System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - Basic Interconnections and Serial Address Options for Four ZL10354s on the Same Bus. . . . . . . . . . 20
Figure 8 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9 - Timing Diagram for the Diversity Bus with DvrClkInv = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
www.DataSheeFt4igUu.croem11 - MPEG Output Data Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15 - External Clocking via AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Zarlink Semiconductor Inc.

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ZL10354 arduino
ZL10354
Data Sheet
2.0 Functional Description
A functional block diagram of the ZL10354 OFDM demodulator is shown in Figure 3. This accepts an IF analog
signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and
frequency synchronization operations are all digital and there are no analog control loops except the AGC. The
frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to
combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,
the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC
can be switched from one stream to another with minimal interruption to the transport stream.
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Figure 3 - OFDM Demodulator Diagram
The FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder
separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to
provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures
minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi
and Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at
the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting
intervals of these are programmable over a very wide range.
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Zarlink Semiconductor Inc.

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