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PDF MAX9420 Data sheet ( Hoja de datos )
| Número de pieza | MAX9420 | |
| Descripción | (MAX9420 - MAX9423) Quad Differential LVECL-to-LVPECL Translators | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2285; Rev 0; 1/02
Quad Differential LVECL-to-LVPECL Translators
General Description
The MAX9420–MAX9423 are extremely fast, low-skew
quad LVECL-to-LVPECL translators designed for high-
speed signal and clock driver applications. The
devices feature ultra-low propagation delay of 336ps
and channel-to-channel skew of 17ps.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, deter-
mined by the state of the SEL input. An enable input
provides the ability to force all the outputs to a differen-
tial low state.
These devices operate with a negative supply voltage
of -2.0V to -3.6V, compatible with LVECL input signals.
The positive supply range is 2.375V to 3.6V for differen-
tial LVPECL output signals.
A variety of input and output terminations are offered for
maximum design flexibility. The MAX9420 has open
inputs and open-emitter outputs. The MAX9421 has
open inputs and 50Ω series outputs. The MAX9422 has
100Ω differential input impedance and open-emitter
outputs. The MAX9423 has 100Ω differential input
impedance and 50Ω series outputs.
The MAX9420–MAX9423 are specified for operation
from -40°C to +85°C, and are offered in space-saving
32-pin 5mm ✕ 5mm TQFP and 32-lead 5mm ✕ 5mm
QFN packages.
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Functional Diagram appears at end of data sheet.
Features
o >500mV Differential Output at 3.0GHz Clock
o 336ps (typ) Propagation Delay in Asynchronous
Mode
o 17ps (typ) Channel-to-Channel Skew
o Integrated 50Ω Outputs (MAX9421/MAX9423)
o Integrated 100Ω Inputs (MAX9422/MAX9423)
o Synchronous/Asynchronous Operation
Ordering Information
PART
TEMP
RANGE
PIN-
DATA
PACKAGE INPUT
OUTPUT
MAX9420EHJ -40°C to +85°C 32 TQFP Open Open
MAX9420EGJ* -40°C to +85°C 32 QFN
MAX9421EHJ -40°C to +85°C 32 TQFP
MAX9421EGJ* -40°C to +85°C 32 QFN
MAX9422EHJ -40°C to +85°C 32 TQFP
MAX9422EGJ* -40°C to +85°C 32 QFN
MAX9423EHJ -40°C to +85°C 32 TQFP
MAX9423EGJ* -40°C to +85°C 32 QFN
Open
Open
Open
100Ω
100Ω
100Ω
100Ω
Open
50Ω
50Ω
Open
Open
50Ω
50Ω
*Future product—contact factory for availability.
Pin Configurations
TOP VIEW
32 31 30 29 28 27 26 25
VEE 1
SEL 2
SEL 3
CLK 4
CLK 5
EN 6
EN 7
VEE 8
MAX9420
MAX9421
MAX9422
MAX9423
24 VCC
23 OUT1
22 OUT1
21 GND
20 GND
19 OUT2
18 OUT2
17 VCC
9 10 11 12 13 14 15 16
TQFP (5mm x 5mm)
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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Quad Differential LVECL-to-LVPECL Translators
Pin Description
PIN
1, 8
2
3
4
5
6
7
9
10
11, 17,
24, 30
12
13
14, 20,
21, 27
15
16
18
19
22
23
25
26
28
29
31
32
—
NAME
VEE
SEL
SEL
CLK
CLK
EN
EN
IN3
IN3
VCC
OUT3
OUT3
GND
IN2
IN2
OUT2
OUT2
OUT1
OUT1
IN1
IN1
OUT0
OUT0
IN0
IN0
EP
FUNCTION
Negative Supply Voltage. Bypass VEE to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four
channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four
channels to operate in synchronous mode.
Inverting Differential Select Input
Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to
the outputs when SEL = differential low.
Noninverting Differential Clock Input
Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the
outputs. Setting EN = low and EN = high (differential low) drives the output low.
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Inverting Differential Output 3
Noninverting Differential Output 3
Ground
Noninverting Differential Input 2
Inverting Differential Input 2
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
Noninverting Differential Input 0
Exposed Paddle (MAX942_EGJ only). Connected to VEE internally. See package dimensions.
_______________________________________________________________________________________ 5
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Quad Differential LVECL-to-LVPECL Translators
Package Information
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MAX9420.PDF ] | |
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