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ZEN2044F Schematic ( PDF Datasheet ) - Zenic

Teilenummer ZEN2044F
Beschreibung 33MHz Up/down Counter
Hersteller Zenic
Logo Zenic Logo 




Gesamt 25 Seiten
ZEN2044F Datasheet, Funktion
www.DataSheet4U.com
PROGRAMMABLE UNIVERSAL COUNTER
ZEN2044F
DESCRIPTION
The ZEN2044F is a 24bit x 4ch. programmable universal counter LSI. The ZEN2044F can count
phase-shifted pulse signals or up/down pulse signals generated from rotary encoders or linear scales.
Since the counter response speed is as high as 33MHz(MAX), the ZEN2044F can be used in a variety of
applications required high speed counting, including digital servo controls and precision measurements. As
to command sets, the ZEN2044F has a compatibility with the ZEN2011P.
The ZEN2044F can also monitor input signals and detect any abnormal input accompanied with noise or
other disturbances, so that the reliability of counted values are secured.
1. Features
Pin Configuration(Top View)
24bit binary up/down counter x 4ch.
Counter response speed:
33MHz(MAX)(CLK fo=33MHz at 50% duty)
Input frequency of count pulse
Two phase-shifted pulse signal input:
DC-8.25MHz (less than fo x 1/4)
Up/down pulse signal input:
DC-16.5MHz (less than fo x 1/2)
Direction recognition for up/down count
Abnormal input detection circuit
80
81
Z/CLR2
UD/AB2
DIR2
Vdd
EXTB3
EXTA3
Vss
LD3
LT3
Vss
Vdd
SEL30
SEL31
SEL32
Vss
A/UP3
B/DN3
Z/CLR3
Vdd
n.c.
80
85
90
95
100
100
75
5
70
10
65
15
60
20
55
25
51
50
50 n.c.
Vss
TEST1
TEST0
Vss
45 D7
D6
D5
D4
Vdd
40 Vss
D3
D2
D1
D0
35 Vdd
RD
WR
Vss
30 n.c.
31
Preload register for the up/down counter
1
30
Latch register for the up/down counter
Coincidence detection between reference value and count value
Counter operation mode
Quad/double/single edge evaluation(for two phase-shifted signal / single pulse signal)
Counter direction selection
Count clear control: synchronous/asynchronous
Command mode
Mode 0:
Each channel has one comparator for coincidence detection
Each channel has one port for user input
Mode 1:
Each channel has two comparators for coincidence detection
Each channel has no port for user input
Logical sum output of coincidence detections available
Interrupt output under some conditions available
8bit data bus
Low power CMOS technology
TTL level compatible input
Single 5V power supply
100 pin QFP
Note ) In following chapters;
"n" corresponds to a number of the channel(0-3).
"*" stands for "Don't care".
(Z2044G00)ZENIC INC.
-1-






ZEN2044F Datasheet, Funktion
www.DataSheet4U.com
4. Operation
The opration of the ZEN2044F is controled by the system software. To use this counter, it is necessary
to specify "command words","counter reference value(if necessary)" and "preloaded value(if necessary)".
Since the entire control circuit woks synchronously, the operations about registers(i.e. data read/write,
command write and status read) can be carried out even if the counter is working.
Each channel can be programed separately because the ZEN2044F has four fully independent sets of
the counter and the registers.
4-1. CPU Interface
The CPU can access the ZEN2044F with AD/CE3-0, C/D, RD and WR. The ZEN2044F has following
two modes for selecting the target channel. The mode depends on DRCTCE.
4-1-1. Direct Channel Enable Mode(DRCTCE="1")
In this mode, AD/CEn is used as the channel enable input for channel n . So multiple channels can
be accessd at a time(write operation only).
Table 2
DRCTCE AD/CE3 AD/CE2 AD/CE1 AD/CE0 C/D RD WR
Function
1 1 1 1 1 * * * Disable(data bus: High-impedance)
1 1 1 1 0 0 0 1 Read: latch register(ch.0)
1 1 1 0 1 0 0 1 Read: latch register(ch.1)
1 1 0 1 1 0 0 1 Read: latch register(ch.2)
1 0 1 1 1 0 0 1 Read: latch register(ch.3)
1 * * * 0 0 1 0 Write: data for registers(ch.0)
1 * * 0 * 0 1 0 Write: data for registers(ch.1)
1 * 0 * * 0 1 0 Write: data for registers(ch.2)
1 0 * * * 0 1 0 Write: data for registers(ch.3)
1 1 1 1 0 1 0 1 Read: status register(ch.0)
1 1 1 0 1 1 0 1 Read: status register(ch.1)
1 1 0 1 1 1 0 1 Read: status register(ch.2)
1 0 1 1 1 1 0 1 Read: status register(ch.3)
1 * * * 0 1 1 0 Write: command(ch.0)
1 * * 0 * 1 1 0 Write: command(ch.1)
1 * 0 * * 1 1 0 Write: command(ch.2)
1 0 * * * 1 1 0 Write: command(ch.3)
ZEN2044F
(Z2044G00)ZENIC INC.
-6-

6 Page









ZEN2044F pdf, datenblatt
www.DataSheet4U.com
5-1. Access pointer
Before you write a data to a certain register, you should set an access pointer properly. But the
ZEN2044F has an auto-incremental function of the access pointer. So when you write data in the
following sequence, what you have to set is only a starting point. Also when reading the latch register,
the target byte(low, middle or high) is changed automatically.
Fig.2
For writes
Counter(low byte)[default at reset]
Counter(middle byte)
Counter(high byte)
Reference reg.A(low byte)
Reference reg.A(middle byte)
Reference reg.A(high byte)
Preload reg.(low byte)
Preload reg.(middle byte)
Preload reg.(high byte)
In Mode 0
Reference reg.B(low byte)
Reference reg.B(middle byte)
Reference reg.B(high byte)
In Mode 1
For reads
Latch reg.(low byte)[default at reset]
Latch reg.(middle byte)
Latch reg.(high byte)
- 12 -
(Z2044G00)ZENIC INC.

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