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ZEN2002AP Schematic ( PDF Datasheet ) - Zenic

Teilenummer ZEN2002AP
Beschreibung High Speed 24bit Up/down Counter
Hersteller Zenic
Logo Zenic Logo 




Gesamt 15 Seiten
ZEN2002AP Datasheet, Funktion
www.DataSheet4U.com
ZEN2002AP
P ROGRAMMABLE UNIVE RSAL COUNTE R
Description
ZENIC INC. ZEN2002AP is a 24 bit pr ogr a m m a ble u n iver sa l cou n t er LSI .
TH E ZEN2002AP cou n t s ph a se-sh ift ed sign a ls a n d u p/down pu lse sign a ls, gen er a t ed fr om r ot a r y en coder s or
lin ea r sca les.
Sin ce t h e cou n t er r espon se speed is a s h igh a s 20MH z(MAX),t h e ZEN2002AP is u sed in a va r iet y of h igh speed
ser vices in clu din g digit a l ser vo con t r ol a n d pr ecision m ea su r em en t .
TH E ZEN2002AP is pr ovided wit h a fu n ct ion wh ich m on it or s t h e in pu t sign a ls a n d det ect s a n y a bn or m a l in pu t
a ccom pa n ied wit h n oise or ot h er dist u r ba n ces, so t h a t t h e r elia bilit y of cou n t ed va lu es a r e secu r ed.
1, Features
24 bit bin a r y u p/down cou n t er .
Cou n t er r espon se speed:
20MH z.(MAX.) ( CLK f0 = 20MH z a t 50% du t y)
In pu t fr equ en cy of cou n t pu lse.
P h a se-sh ift ed sign a l in pu t :
A/B ph a se in pu t DC ~ 5MH z.
(less t h a n f0 ~ 1/4)
U p/down pu lse sign a l in pu t :
U p/down in pu t DC ~ 10MH z
(less t h a n f0 ~ 1/2)
CLK fr equ en cy DC ~ 20MH z.
(MAX.: du t y r a t io 50%)
Dir ect ion r ecogn it ion for u p/down cou n t in g.
Abn or m a l in pu t det ect ion cir cu it .
P r eloa d r egist er for t h e u p/down cou n t er .
La t ch r egist er for t h e u p/down cou n t er .
Refer en ce va lu e - cou n t va lu e coin ciden ce
det ect ion fu n ct ion .
Mom en t a r y ou t pu t : TTL
In t er r u pt ou t pu t (la t ch ed) : open collect or
On -ch ip st a t u s r egist er .
Cou n t er oper a t ion m ode.
E dge eva lu a t ion select ion : sin gle/dou ble/qu a d
(on ly for ph a se-sh ift ed sign a l in pu t )
Cou n t dir ect ion select ion .
Cou n t er clea r con t r ol:syn ch r on ou s/
a syn ch r on ou s clea r .
F ixed/va r ia ble edge clea r .
8 bit data bus.
Low power CMOS t ech n ology.
TTL com pa t ible.
Sin gle 5V power su pply.
28 pin DIP.
2, Typical Applications
NC m a ch in e t ools
P r ecision posit ion er s
Robot a r m con t r oller s
Speed con t r oller s for r ot a t in g m a ch in es
E lect r on ic ga u ges
F r equ en cy cou n t er s
Pin configuration
(Top view)
VSS
CLK
RESET
CE
C/D
RD
WR
LD
LT
D0
D1
D2
D3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
INT
EQ
UD/AB
DIR
VSS
A/UP
B/DN
Z/CLR
D7
D6
D5
D4
VDD
ZENIC Inc.
-1-






ZEN2002AP Datasheet, Funktion
www.DataSheet4U.com
7, Command register
ZEN2002AP
D7 D6 D5 D4 D3 D2 D1 D0
| | (command ID)
0 0 = Load/latch and register selection
0 1 = Phase-Z input control
1 0 = Edge evaluation and clearness timing control
1 1 = Interruption output control
(1) Latch and loading/register selection
D7 D6 D5 D4 D3 D2 D1 D0
0 0 LD LT RS1 RS0 BS1 BS0
| | | | 0 0 -- Lower 8 bits. (D) ( the pointer is automatically incremented )
| | | | 0 1 -- Middle 8 bits.
Π
| | | | 1 0 -- Upper 8 bits.
Π
| | 0 0 --------------- Up/down counter (D) ( the pointer is automatically incremented )
| | 0 1 --------------- Comparison register
Π
| | 1 - ---------------- Preload register
Π
| 1 ------------------------ The data latch instruction
1 ---------------------------------- The data loading instruction
(2) Phase-Z input control
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 - - ZE1 ZE0
0 0 -- No operation
0 1 -- Phase-Z input invalidity (D)
1 0 -- Limiting phase-Z input next effective
1 1 -- Every time, phase-Z input is effective.
(3) Edge evaluation and clear timing
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 SYNC ZC MS1 MS0
| | 0 0 -- Single
| | 0 1 -- Double
| | 1 - -- Quad (D)
| 0 ------------- A changeable edge is clear.
| 1 ------------- A fixed edge is clear (D).
0 ------------------- Asynchronous clearness (D)
1 ------------------- Synchronous clearness
(4) Interruption output control
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 - - - INT
0 ---- Interruption output disable (D)
1 ---- Interruption output enable
(D): Default
ZENIC Inc.
-6-

6 Page









ZEN2002AP pdf, datenblatt
www.DataSheet4U.com
Phase-shifted pulse input
tPWABH
A/UP
tSAB
tSAB
tPWABL
tSAB
tSAB
ZEN2002AP
B/DN
tPWABH
tPWABL
Z/CLR
(Synchronous clear)
t tSZ SZ
Z/CLR
(Asynchronous clear)
tZZ
Up/down pulse input
A/UP
B/DN
tDNH
tDNL
tUPL
tUPH
Output timing of EQ,INT signal
CLK
UDC (SP-1)
(SP)
EQ
INT
(SP+1)
(SP+2)
t tEQF EQR
tINTF
UDC:count value of up/down counter
(SP):set value of reference register
- 12 -
ZENIC Inc.

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