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ML145428 Schematic ( PDF Datasheet ) - LANSDALE Semiconductor

Teilenummer ML145428
Beschreibung Asynchronous-to-Synchronous and Synchronous-to-Asynchronous Converter
Hersteller LANSDALE Semiconductor
Logo LANSDALE Semiconductor Logo 




Gesamt 14 Seiten
ML145428 Datasheet, Funktion
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ML145428
Asynchronous–to–Synchronous
and Synchronous–to–
Asynchronous Converter
Legacy Device: Motorola MC145428
The ML145428 Data Set Interface provides asynchronous-to-synchronous
and synchronous-to-asynchronous data conversion. It is ideally suited for
voice/data digital telesets supplying an EIA-232 compatible data port into a
synchronous transmission link. Other applications include: data multiplexers,
concentrators, data-only switching, and PBX-based local area networks. This
low-power CMOS device directly interfaces with either the 64 kbps or 8kbps
channel of Motorola’s MC145422 and MC145426 Universal Digital Loop
Transceivers (UDLTs), as well as the MC145421 and MC145425 Second
Generation Universal Digital Loop Transceivers (UDLT II).
• Provides the Interface Between Asynchronous Data Ports and
Synchronous Transmission Lines
• Up to 128 kbps Asynchronous Data Rate Operation
• Up to 2.1 Mbps Synchronous Data Rate Operation
• On-Board Bit Rate Clock Generator with Pin Selectable Bit Rates of
300, 1200, 1400, 4800, 9600, 19200 and 38400 bps or an Externally
Supplied 16 Times Bit Rate Clock
• Accepts Asynchronous Data Words of 8 or 9 Bits in Length
• False Start Detection Provided
• Automatic Sync Insertion and Checking
• Single 5 V Power Supply
• Low Power Consumption of 5 mW Typical
• Application Notes AN943 and AN946
• Operating Temperature Range TA = –40º to +85ºC.
TxS
TxD
DL
BR1-BR3
BCLK
BRCLK
BLOCK DIAGRAM
DATA
STRIPPER
BAUD
RATE
GEN
Tx
FIFO
SYNCHRONOUS
CHANNEL
TRANSMITTER
DCO
CONTROL
DOE
DIE
DCLK
CM
RESET
20
1
P DIP 20 = RP
PLASTIC
CASE 732
SOG 20 = -6P
20 PLASTIC
CASE 751D
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20
MC145428P ML145428RP
MC145428DW ML145428-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
TxS 1
TxD 2
DL 3
BRCLK 4
BCLK 5
BR1 6
BR2 7
BR3 8
SB 9
VSS 10
20 VDD
19 RESET
18 DCO
17 DOE
16 CM
15 DCLK
14 DIE
13 DCI
12 RxS
11 RxD
RxD DATA
Rx SYNCHRONOUS
SB
FORMATTER
FIFO
CHANNEL
RECEIVER
DCI
RxS
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ML145428 Datasheet, Funktion
ML145428
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LANSDALE Semiconductor, Inc.
CIRCUIT DESCRIPTION
The ML145428 Data Set Interface provides a means for con-
version of an asynchronous (start/stop format) data channel to
a synchronous data channel and synchronous to asynchronous
data channel conversion. Although primarily intended to facili-
tate the implementation of RS - 232 compatible asynchronous
data ports in digital telephone sets using the MC145422/26
UDLTs, this device is also useful in many applications that
require the conversion of synchronous and asynchronous data.
TRANSMIT CIRCUIT
Asynchronous data is input on the TxD pin. This data is
expected to consist of a start bit (logic low) followed by eight
or nine data bits and one or more stop bits (logic high). The
length of the data word is selected by the DL pin. The data
baud rate is selected with the BR1, BR1 and BR3 pins to
obtain the internal sampling clock. This internal sampling
clock is selected to be 16 times the baud rate at the TxD pin.
An externally supplied 16 times clock may also be used, in
which case the BR1, BR2, and BR3 pins should all be at logic
zero and the 16 times sampling clock supplied at the BC pin.
Data input at the TxD pin is stripped of start and stop bits
and is loaded into a four–word deep FIFO register. A break
condition is also recognized at the TxD pin and this informa-
tion is relayed to the synchronous channel transmitter which
codes this condition so it may be re–created at the remote
receiving device.
The synchronous channel transmitter sends one bit at a time
under control of the DC, CM and DOE pins. The synchronous
channel transmitter transmits one of three possible data pat-
terns based on whether or not the top of the Tx FIFO is full
and whether or not a break condition has been recognized by
the data stripper. When no data is available at the top of the Tx
FIFO for transmission, the synchronous data transmitter sends
a special synchronizing flag pattern (011111110). When a
break condition is detected by the data stripper and no data is
available at the top of the Tx FIFO, the break pattern
(111111110) is sent. Figure 2A depicts this operation.
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ML145428 pdf, datenblatt
ML145428
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LANSDALE Semiconductor, Inc.
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