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PDF ML145170 Data sheet ( Hoja de datos )
| Número de pieza | ML145170 | |
| Descripción | Phase-Frequency Detector PLL Frequency Synthesizer | |
| Fabricantes | LANSDALE Semiconductor | |
| Logotipo |  |
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ML145170
Phase–Frequency Detector
PLL Frequency Synthesizer
with Serial Interface
Legacy Device: Motorola/Freescale MC145170-2
The Lansdale ML145170 is a single–chip synthesizer capable of direct
usage in the MF, HF and VHF bands. A special architecture makes this
PLL easy to program. Either a bit– or byte–oriented format may be used.
Due to the patented BitGrabber™ registers, no address/steering bits are
required for random access of the three registers. Thus, tuning can be
accomplished via a 2–byte serial transfer to the 16-bit N register.
The device features fully programmable R and N counters, an amplifier
at the fin pin, on–chip support of an external crystal, a programmable ref-
erence output, and both single and double–ended phase detectors with
linear transfer functions (no dead zones). A configuration (C) register
allows the part to be configured to meet various applications. A patented
feature allows the C register to shut off unused outputs, thereby minimiz-
ing noise and interference.
In order to reduce lock times and prevent erroneous data from being
loaded into the counters, a patented jam load feature is included.
Whenever a new divide ratio is loaded into the N register, both the N and
R counters are jam–loaded with their respective values and begin count-
ing down together. The phase detectors are also initialized during the jam
load.
• Operating Voltage Range: 2.7 to 5.5 V
• Operating Temperature Range: TA = –40º to +85º C
• Maximum Operating Frequency:
185 MHz @ Vin = 500 mVpp, 4.5 V Minimum Supply
100 MHz @ Vin = 500 mVpp, 3.0 V Minimum Supply
• Operating Supply Current:
0.6 mA @ 3.0 V, 30 MHz
1.5 mA @ 3.0 V, 100 MHz
3.0 mA @ 5.0 V, 50 MHz
5.8 mA @ 5.0 V, 185 MHz
• R Counter Division Range: 1 and 5 to 32,767
• N Counter Division Range: 40 to 65,535
• Direct Interface to Motorola SPI Serial Data Port
• See Application Notes AN1207/D and AN1671/D
• See web site www.lansdale.com for ML145170 control software
16
1
P DIP 16 = EP
PLASTIC PACKAGE
CASE 648
16 16
11
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B
TSSOP 16 = -7P
PLASTIC PACKAGE
CASE 948C
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SO 16
TSSOP 16
MC145170P2 ML145170EP
MC145170D2 ML145170-5P
MC145170DT2 ML145170-7P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN CONNECTIONS
φ
φ
BitGrabber™ is a trademark of Motorola/Freescale
Page 1 of 26
www.lansdale.com
Issue A
1 page  
ML145170
www.DataSheet4U.com
Figure 1.
LANSDALE Semiconductor, Inc.
SWITCHING WAVEFORMS
Figure 2.
Figure 3.
Figure 4.
Figure 5. Test Circuit
*Includes all probe and fixtures capacitance.
Figure 6. Test Circuit
Ω
*Includes all probe and fixtures capacitance.
Page 5 of 26
www.lansdale.com
Issue A
5 Page 
ML145170
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LANSDALE Semiconductor, Inc.
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
*At this point, the new byte is transferred to the C register and stored. No other registers
are affected.
C7–POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts
PDout and interchanges the φR funtion with φV as depicted in Figure 17. Also see the phase
detector output pin description for more information. This bit is cleared low at power up.
C6–PDA/B:
Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing φR
and φV to the static high state. When cleared low, phase/frequency detector B is enabled (φ R
and φV) and phase/frequency detector A is disabled with PDout forced to the high–impedance
state. This bit is cleared low at power up.
C5–LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is
forced to a static low level. This bit is cleared low at power up.
C4–C2, OSC2–OSC0: Reference output controls which determine the REFout characteristics as shown below. Upon
power up, the bits are initialized such that OSCin/8 is selected.
C4 C3 C2 REFout Frequency
0 0 0 DC (Static Low)
0 0 1 OSCin
0 1 0 OSCin /2
0 1 1 OSCin /4
1 0 0 OSCin /8 (POR Default)
1 0 1 OSCin /16
1 1 0 OSCin /8
1 1 1 OSCin /16
C1–fVE: Enables the fV output when set high. When cleared low, the fV output is forced to a static low
level. The bit is cleared low upon power up.
C0–fRE: Enables the fR output when set high. When cleared low, the fR output is forced to a static low
level. The bit is cleared low upon power up.
Page 11 of 26
www.lansdale.com
Issue A
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ML145170.PDF ] | |
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