PDF ML145162 Data sheet ( Hoja de datos )

Número de pieza	ML145162
Descripción	60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS
Fabricantes	LANSDALE Semiconductor
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No Preview Available ! www.DataSheet4U.com ML145162 60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS Legacy Device: Motorola MC145162 The ML145162 is a dual phase–locked loop (PLL) frequency synthesizer especially designed for CT–1 cordless phone applications worldwide. This frequency synthesizer is also for any product with a frequency operation at 60MHz or below. The device features fully programmable receive, transmit, reference, and auxiliary reference counters accessed through an MCU serial interface. This feature allows this device to operate in any CT–1 cordless phone application. The device consists of two independent phase detectors for transmit and receive loops. A common reference oscillator, driving two independent refer- ence frequency counters, provides independent reference frequencies for transmit and receive loops. The auxiliary reference counter allows the user to select an additional reference frequency for receive and transmit loops if required. • Operating Voltage Range: 2.5 to 5.5 V • Operating Temperature Range: TA = – 40 to +75°C • Operating Power Consumption: 3.0 mA @ 2.5 V • Maximum Operating Frequency: 60 MHz @ 200 mV p–p, VDD = 2.5 V • Three or Four Pins Used for Serial MCU Interface • Built–In MCU Clock Output with Frequency of Reference Oscillator ÷3/÷4 • Power Saving Mode Controlled by MCU • Lock Detect Signal • On–Chip Reference Oscillator Supports External Crystals to 16.0 MHz • Reference Frequency Counter Division Range: 16 to 4095 • Auxiliary Reference Frequency Counter Division Range: 16 to 16,383 • Transmit Counter Division Range: 16 to 65,535 • Receive Counter Division Range: 16 to 65,535 16 1 P DIP 16 = EP PLASTIC DIP CASE 648 16 1 SOG 16 = -5P SOG PACKAGE CASE 751B CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 16 SOG 16 MC145162P ML145162EP MC145162D ML145162-5P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENT CLK ADin Din ENB MCUCLK VSS OSCin OSCout 1 2 3 4 5 6 7 8 16 LD 15 TxPDout 14 fin–T 13 TxPS/fTx 12 VDD 11 RxPS/FRx 10 RxPDout 9 fin–R Page 1 of 24 www.lansdale.com Issue 0 1 page ML145162 www.DataSheet4U.com LANSDALE Semiconductor, Inc. tTLH ANY OUTPUT 90% 10% Figure 1. SWITCHING WAVEFORMS tTHL tr CLK, OSCin, fin–T, fin–R 90% 10% Figure 2. tf ENB, CLK tw 50% Figure 3. CLK tsu1 ENB FIRST CLK LAST CLK th1 VDD VSS VDD VSS Figure 4. ENB High During Serial Transfer ADin, Din 50% tsu th CLK 50% LAST CLK FIRST CLK tsu ENB 50% PREVIOUS DATA LATCHED trec VDD VSS VDD VSS VDD VSS Figure 5. ENB Low During Serial Transfer Page 5 of 24 www.lansdale.com Issue 0 5 Page ML145162 www.DataSheet4U.com LANSDALE Semiconductor, Inc. ADin 16–BIT Tx COUNTER DIVDE RATIO Din 16–BIT Rx COUNTER DIVIDE RATIO CLK LAST CLOCK ENB NOTE: ENB must be low during the serial transfer. Figure 15. Programming Format for Transmit and Receive Counters (4–Pin Interfacing Scheme) Table 3. Global CT–1 Reference Frequency Setting vs Channel Frequencies Country U.S.A. Channels Frequency 46/49 MHz (10, 15, 25 Channels) fR1 5.0 kHz fR2 — France 26/41 MHz 6.25 kHz/12.5 kHz — Spain 31/41 MHz 5.0 kHz — Australia 30/39 MHz 5.0 kHz — U.K. 1.7/47 MHz 6.25 kHz 1.0 kHz New Zealand 1.7/34/40 MHz 6.25 kHz 1.0 kHz REFERENCE FREQUENCY SELECTION AND PROGRAMMING Figure 16 shows the bit function of the reference frequency programming word. The user can either select the “fixed” ref- erence frequency for all channels accordingly or provide a spe- cific reference frequency for a particular channel by using two reference frequency counters (e.g., for an application in France, the base set transmit channel common fixed reference frequency is 6.25 kHz or 12.5 kHz). (See Table 3 and Figure 6 for reference frequencies for various countries.) However, transmit channels 6, 8, and 14 can be set to 25 kHz, and chan- nel 8 reference frequency can be set to 50 kHz. But this refer- ence frequency may not be applied to the receiving side; there- fore, the receiving side reference frequency must be generated by another reference frequency counter. The higher the refer- ence frequency, the better the phase noise performance and faster the lock time, but the PLL consumes more current if both reference frequency counters are in operation. In general, the 12–bit reference frequency counter plus the ÷ 4 and ÷ 25 module can offer all the reference frequencies for global CT–1 transmit and receive channel requirements. Users can select their own reference frequency by introducing the additional 14–bit auxiliary reference frequency counter. Again, the 14–bit auxiliary reference frequency counter can be shut down by the auxiliary reference enable bit in the refer- ence counter programming word by setting the bit to 0. At this state, the fR2 is automatically connected to point C (the ÷25 block output), and fR1 can be connected to point A or B by setting the fR1–S1 and fR1–S2 bits in the reference counter program word. The 14–bit auxiliary reference frequency count- er data will be in “Don’t Care” state. If the 14–bit auxiliary reference frequency counter is enabled (auxiliary reference enable = 1), then fR2 is automatically con- nected to point D (14–bit counter output), and fR1 can be selected to connect to point A, B, or C, depending on the bit setting of fR1–S1 and fR1–S2. Table 4 and Figure 16 describe the functions of the auxiliary reference enable bit and the fR1–S1 and fR1–S2 bits selection. Page 11 of 24 www.lansdale.com Issue 0 11 Page

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