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PDF ML145051 Data sheet ( Hoja de datos )
| Número de pieza | ML145051 | |
| Descripción | (ML145050 / ML145051) 10-Bit A/D Converter | |
| Fabricantes | LANSDALE Semiconductor | |
| Logotipo |  |
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ML145050
ML145051
10-Bit A/D Converter
with Serial Interface - CMOS
Legacy Device: Motorola MC145050, MC145051
These ratio metric 10-bit ADCs have serial interface ports to provide
communication with MCUs and MPUs. Either a 10- or 16-bit format
can be used. The 16-bit format can be one continuous 16-bit stream or
two intermittent 8-bit streams. The converters operate from a single
power supply with no external trimming required. Reference voltages
down to 4.0 V are accommodated.
The ML145050 has the same pin out as the 8-bit ML145040 which
allows an external clock (ADCLK) to operate the dynamic A/D con-
version sequence. The ML145051 has the same pin out as the 8-bit
ML145041 which has an internal clock oscillator and an end-of-con-
version (EOC) output.
• 11 Analog Input Channels with Internal Sample-and-Hold
• Operating Temperature Range: – 40 to 125°C
• Successive Approximation Conversion Time:
ML145050 – 21 µs (with 2.1 MHz ADCLK)
ML145051 – 44 µs Maximum
• Maximum Sample Rate:
ML145050 – 38 ks/s
ML145051 – 20.4 ks/s
• Analog Input Range with 5-Volt Supply: 0 to 5 V
• Monotonic with No Missing Codes
• Direct Interface to Motorola SPI and National MICROWIRE
Serial Data Ports
• Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible
• Low Power Consumption: 14 mW
• Chip Complexity: 1630 Elements (FETs, Capacitors, etc.)
• See Application Note AN1062 for Operation with QSPI
P DIP 20 = RP
PLASTIC
CASE 738
SO 20W = -6P
SOG
CASE 751D
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20W
P DIP 20
SOG 20W
MC145050P
MC145050DW
MC145051P
MC145051DW
ML145050RP
ML145050-6P
ML145051RP
ML145051-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
*ADCLK (ML145050); EOC (ML145051)
AN0 1
AN1 2
AN2 3
AN3 4
AN4 5
AN5 6
AN6 7
AN7 8
AN8 9
VSS 10
20 VDD
19 *
18 SCLK
17 Din
16 Dout
15 CS
14 Vref
13 VAG
12 AN10
11 AN9
MICROWARE is A Trademark Of National Semiconductor Corp.
Page 1 of 15
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Issue B
1 page  
ML145050, ML145051
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LANSDALE Semiconductor, Inc.
tf
2.0 V
SCLK
th
Dout
twL twH
tr
0.8 V
1/f
tPLH, tPHL
2.4 V
0.4 V
tTLH, tTHL
Figure 1.
SWITCHING WAVEFORMS
CS
Dout
0.8 V
tPZH, tPZL
2.4 V
0.4 V
2.0 V
tPHZ, tPLZ
90%
10%
Figure 2.
Din
SCLK
VALID
2.0 V
0.8 V
th
tsu
2.0 V
0.8 V
Figure 3.
EOC
0.4 V
tTLH
2.4 V
td
Dout
2.4 V
0.4 V
VALID MSB
NOTE: Dout is driven only when CS is active (low).
Figure 4.
CS
SCLK
0.8 V
tsu
FIRST
0.8 V CLOCK
2.0 V
th
LAST
CLOCK 0.8 V
Figure 5.
VDD
TEST
POINT
2.18 k
Dout
DEVICE
UNDER
TEST
12 k 100 pF
SCLK
EOC
10TH
CLOCK
0.8 V
2.4 V
tTHL
tPHL
0.4 V
Figure 6.
VDD
TEST
POINT
2.18 k
EOC
DEVICE
UNDER
TEST
12 k 50 pF
Figure 7. Test Circuit
Figure 8. Test Circuit
Page 5 of 15
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Issue B
5 Page 
ML145050, ML145051
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LANSDALE Semiconductor, Inc.
Legacy Applications Information
DESCRIPTION
This example application of the ML145050/ML145051
ADCs interfaces three controllers to a microprocessor and
processes data in real-time for a video game. The standard joy-
stick X-axis (left/right) and Y-axis (up/down) controls as well
as engine thrust controls are accommodated.
Figure 15 illustrates how the ML145050/ML145051 is used
as a cost-effective means to simplify this type of circuit design.
Utilizing one ADC, three controllers are interfaced to a CMOS
or NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor's
MICROWIRE serial port may also be used. Full duplex opera-
tion optimizes throughput for this system.
DIGITAL DESIGN CONSIDERATIONS
and electrical environment. This should be verified during pro-
totyping with an oscilloscope. If shielding is required, a twist-
ed pair or foil-shielded wire (not coax) is appropriate for this
low frequency application. One wire of the pair or the shield
must be VAG.
A reference circuit voltage of 5 volts is used for this applica-
tion. The reference circuitry may be as simple as tying VAG to
system ground and Vref to the system's positive supply. (See
Figure 16.) However, the system power supply noise may
require that a separate supply be used for the voltage reference.
This supply must provide source current forVref as well as
current for the controller potentiometers.
A bypass capacitor of approximately 0.22 µF across the Vref
and VAG pins is recommended. These pins are adjacent on the
ADC package which facilitates mounting the capacitor very
close to the ADC.
Motorola's MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs maybe
used if power consumption is not critical. A VDD or VSS 0.1
µF bypass capacitor should be closely mounted to the ADC.
Both the ML145050 and ML145051 accommodate all the
analog system inputs. The ML145050, when used with a 2
MHz MCU, takes 27 µs to sample the analog input, perform
the conversion, and transfer the serial data at 2 MHz. Forty-
four ADCLK cycles (2 MHz at input pin 19) must be provided
and counted by the MCU before reading the ADC results. The
ML145051 has the end-of-conversion (EOC) signal (at output
pin 19) to define when data is ready, but has a slower 49 µs
cycle time. However, the 49 µs is constant for serial data rates
of 2 MHz independent of the MCU clock frequency. Therefore,
the ML145051 may be used with the CMOS MCU operating at
reduced clock rates to minimize power consumption without
severely sacrificing ADC cycle times, with EOC being used to
generate an interrupt. (The ML145051 may also be used with
MCUs which do not provide a system clock.)
ANALOG DESIGN CONSIDERATIONS
Controllers with output impedances of less than 1 kΩ maybe
directly interfaced to these ADCs, eliminating the need for
buffer amplifiers. Separate lines connect the Vref and VAG
pins on the ADC with the controllers to provide isolation from
system noise.
Although not indicated in Figure 15, the Vref and controller
output lines may need to be shielded, depending on their length
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straight forward. The
nine analog inputs, AN0 through AN8, are scanned by reading
the analog value of the previously addressed channel into the
MCU and sending the address of the next channel to be read to
the ADC, simultaneously.
If the design is realized using the ML145050, 44 ADCLK
cycles (at pin 19) must be counted by the MCU to allow time
for A/D conversion. The designer utilizing the MC145051 has
the end-of-conversion signal (at pin 19) to define the conver-
sion interval. EOC may be used to generate an interrupt, which
is serviced by reading the serial data from the ADC. The soft-
ware flow should then process and format the data, and transfer
the information to the video circuitry for updating the display.
When these ADCs are used with a 16-bit (2-byte) transfer,
there are two types of offsets involved. In the first type of off-
set, the channel information sent to the ADCs is offset by 12
bits. That is, in the 16-bit stream, only the first 4 bits (4 MSBs)
contain the channel information. The balance of the bits are
don't cares. This results in 3 don't-care nibbles, as shown in
Table 2. The second type of offset is in the conversion result
returned from the ADCs; this is offset by 6 bits. In the 16-bit
stream, the first 10 bits (10 MSBs) contain the conversion
results. The last 6 bits are zeroes. The hexadecimal result is
shown in the first column of Table 3. The second column shows
the result after the offset is removed by a microprocessor rou-
tine. If the 16-bit format is used, these ADCs can transfer one
continuous 16-bit stream or two intermittent 8-bitstreams.
Page 11 of 15
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Issue B
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ML145051.PDF ] | |
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