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ML145040 Schematic ( PDF Datasheet ) - LANSDALE Semiconductor

Teilenummer ML145040
Beschreibung (ML145040 / ML145041) 8-Bit A/D Converters
Hersteller LANSDALE Semiconductor
Logo LANSDALE Semiconductor Logo 




Gesamt 12 Seiten
ML145040 Datasheet, Funktion
www.DataSheet4U.com
ML145040
ML145041
8-Bit A/D Converters With
Serial Interface
Silicon-Gate CMOS
SEMICONDUCTOR TECHNICAL DATA
Legacy Device: Motorola MC145040, MC145041
The ML145040 and ML145041 are low-cost 8-bit A/D Converters with
serial interface ports to provide communication with microprocessors and
microcomputers. The converters operate from a single power supply with a
maximum nonlinearity of ± 1/2 LSB over the full temperature range. No
external trimming is required.
The ML145040 allows an external clock input (A/D CLK) to operate the
dynamic A/D conversion sequence. The ML145041 has an internal clock
and an end–of–conversion signal (EOC) is provided.
• Operating Voltage Range: VDD = 4.5 to 5.5 Volts
• Successive Approximation Conversion Time:
ML145040 – 10 µs (with 2 MHz A/D CLK)
ML145041 – 20 µs Maximum (Internal Clock)
• 11 Analog Input Channels with Internal Sample and Hold
• 0- to 5-Volt Analog Input Range with Single 5-Volt Supply
• Ratiometric Conversion
• Separate Vref and VAG Pins for Noise Immunity
• Wide Vref Range
• No External Trimming Required
• Direct Interface to Motorola SPI and National
MICROWIRE Serial Data Ports
• TTL/NMOS–Compatible Inputs May be Driven with CMOS
• Outputs are CMOS, NMOS or TTL Compatible
• Very Low Reference Current Requirements
• Low Power Consumption: 11 mW
• Internal Test Mode for Self Test
P DIP 20 = RP
CERAMIC PLASTIC
CASE 732 CASE 738
SO 20W = -6P
SOG
CASE 751D
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SO 20W
P DIP 20
SO 20W
MC145040P
MC145040DW
MC145041P
MC145041DW
ML145040RP
ML145040-6P
ML145041RP
ML145041-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Page 1 of 12
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Issue A






ML145040 Datasheet, Funktion
ML145040, ML145041
www.DataSheet4U.com
PIN DESCRIPTIONS
LANSDALE Semiconductor, Inc.
DIGITAL INPUTS AND OUTPUTS
CS (Pin 15)
from the MPU system clock. Deviations from a 50% duty
cycle can be tolerated if each half period is > 238 ns.
Active–low chip select input. CS provides three–state control
of Dout. CS at a high logic level forces Dout to a high–imped-
ance state. IN addition, the device recognizes the falling edge
of CS as a serial interface reset to provide synchronization
between the MPU and the A/D converter’s serial data stream.
To prevent a spurious reset from occurring due to noise on the
CS input, a delay circuit has been included such that a CS sig-
nal of duration 1 A/D CLK period (ML145040) or 500 ns
(ML145041) is ignored. A valid CS signal is acknowledged
when the duration is 3 A/D CLK periods (ML145040) or 3
µs (ML145041)
CAUTION
A reset aborts a conversion sequence, therefore
high–to–low transitions on CS must be avoided dur-
ing the conversion sequence.
Dout (Pin 16)
Serial data output of the A/D conversion result. The 8–bit
serial data stream begins with the most significant bit and is
shifted out on the high–to–low transition of SCLK. Dout is a
three–state output as controlled by CS. However, Dout is
forced into a high–impedance state after the eighth SCLK,
independent of the state of CS. See Figures 9, 10, 11, or 12.
Din (Pin 17)
Serial data input. The 4–bit serial data stream begins with the
most significant address bit of the analog mux and is shifted in
on the low–to–high transition of SCLK.
EOC (Pin 19, ML145041 only)
End–of–conversion output. EOC goes low on the negative
edge of the eighth SCLK. The low–to–high transition of EOC
indicates the A/D conversion is complete and the data is ready
for transfer.
ANALOG INPUTS AND TEST MODE
AN0 through AN10 (Pins 1-9, 11, 12)
Analog multiplexer inputs. The input AN0 is addressed by
loading $0 into the serial data input, Din. AN1 is addressed by
$1, AN2 by $2…AN10 via $A. The mux features a
break–before–make switching structure to minimize noise
injection into the analog inputs. The source impedance driving
these inputs must be 10 k. NOTE: $B addresses an on–chip
test voltage of (Vref + VAG)/2, and produces an output of $80
if the converter is functioning properly. However, a ± 1 LSB
deviation from $80 occurs in the presence of sufficient system
noise (external to the chip) on VDD, VSS, Vref or VAG.
POWER AND REFERENCE PINS
VSS and VDD (Pins 10 and 20)
Device supply pins. VSS is normally connected to digital
ground; VDD is connected to a positive digital supply voltage.
VDD – VSS variations over the range of 4.5 to 5.5 volts do not
affect the A/D accuracy. Excessive inductance in the VDD or
VSS lines as on automatic test equipment, may cause A/D off-
sets > 1/2 LSB.
SCLK (Pin 18)
Serial data clock. THe serial data register is completely stat-
ic, allowing SCLK rates down to DC in a continuos or inter-
mittent mode. SCLK need not be synchronous to the A/D CLK
(ML145040) or the internal clock (ML145041). Eight SCLK
cycles are required for each simultaneous data transfer, the
low–to–high transition shifting in the new address and the
high–to–low transition shifting out the previous conversion
result. The address is acquired during the first four SCLK
cycles, with the interval produced by the remaining four cycles
being used to begin charging the on–chip sample–and–hold
capacitors. After the eighth SCLK, the SCLK input is inhibited
(on–chip) until the conversion is complete.
A/D CLK (Pin 18, ML145040 only)
A/D clock input. This pin clocks the dynamic A/D conver-
sion sequence, and may be asynchronous and unrelated to
SCLK. The signal must be free running, and may be obtained
VAG and Vref (Pins 13 and 14)
Analog reference voltage pins which determine the lower and
upper boundary of the A/D conversion. Analog input voltages
Vref produce an output of $FF and input voltages VAG pro-
duce an output of $00. CAUTION: THe analog input voltage
must be VSS and VDD. The A/D conversion result is ratio-
metric to Vref – VAG as shown by the formula:
Vref and VAG should be as noise–free as possible to avoid
degradation of the A/D conversion. Noise on either of these
pins will couple 1:1 to the analog input signal i.e. a 20 mV
change in Vref can cause a 20 mV error in the conversion
result. Ideally Vref and VAG should be single-point connected
to the voltage supply driving the system’s transducers.
Page 6 of 12
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Issue A

6 Page









ML145040 pdf, datenblatt
ML145040, ML145041
www.DataSheet4U.com
OUTLINE DIMENSIONS
SOG 20W = -6P
(ML145040-6P, ML145041-6P)
-A- CASE 751D-04
20 11
-B- P 10 PL
0.010 (0.25) M B M
1 10
D 20 PL
0.010 (0.25) M T B S
AS
J
F
R X 45°
G 18 PL
C
-T-
SEATING
K PLANE
M
LANSDALE Semiconductor, Inc.
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOW ABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC
0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 12 of 12
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Issue A

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