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ML145155 Schematic ( PDF Datasheet ) - LANSDALE Semiconductor

Teilenummer ML145155
Beschreibung (ML145151 - ML145158) Parallel-Input PLL Frequency Synthesizer Interfaces
Hersteller LANSDALE Semiconductor
Logo LANSDALE Semiconductor Logo 




Gesamt 30 Seiten
ML145155 Datasheet, Funktion
www.DataSheet4U.com
ML145151 ML145156
ML145152 ML145157
ML145155 ML145158
PLL Frequency Synthesizer Family - CMOS
The devices described in this document are typically used as low–power, phase–locked loop frequency
synthesizers. When combined with an external low–pass filter and voltage–controlled oscillator, these
devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the
device's frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used
between the VCO and the synthesizer IC.
These frequency synthesizer chips can be found in the following and other applications:
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two–Way Radios
Amateur Radio
OSC ÷R
CONTROL LOGIC
φ
÷ A ÷N
÷ P/P + 1
VCO
OUTPUT
FREQUENCY
EXTERNAL
COMPONENTS
CONTENTS
Page
DEVICE DETAIL SHEETS
ML145151 Parallel–Input, Single–Modulus ...........................................................................................2
ML145152 Parallel–Input, Dual–Modulus..............................................................................................5
ML145155 Serial–Input, Single–Modulus ..............................................................................................9
ML145156 Serial–Input, Dual–Modulus...............................................................................................13
ML145157 Serial–Input, Single–Modulus ............................................................................................17
ML145158 Serial–Input, Dual–Modulus...............................................................................................20
FAMILY CHARACTERISTICS
Maximum Ratings..................................................................................................................................23
DC Electrical Characteristics.................................................................................................................23
AC Electrical Characteristics.................................................................................................................25
Timing Requirements.............................................................................................................................26
Frequency Characteristics ......................................................................................................................27
Phase Detector/Lock Detector Output Waveforms................................................................................27
DESIGN CONSIDERATIONS
Phase–Locked Loop – Low–Pass Filter Design ....................................................................................28
Crystal Oscillator Considerations ..........................................................................................................29
Dual–Modulus Prescaling......................................................................................................................30
Page 1 of 35
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Issue A






ML145155 Datasheet, Funktion
LANSDALE Semiconductor, Inc.
www.DataSheet4U.com
ML145152 BLOCK DIAGRAM
ML145152
OSCout
OSCin
fin
RA2
RA1 12 x 8 ROM REFERENCE DECODER
RA0
12
12–BIT ÷ R COUNTER
CONTROL
LOGIC
6–BIT ÷ A COUNTER
10–BIT ÷ N COUNTER
LOCK
DETECT
PHASE
DETECTOR
LD
MC
φV
φR
A5 A3 A2 A0
N0 N2 N4 N5 N7 N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the positive edge triggered ÷ N and ÷ A counters.
fin is typically derived from a dual–modulus prescaler and is
AC coupled into the device. For larger amplitude signals (stan-
dard CMOS logic levels) DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The total
reference divide values are as follows:
Reference Address Code
RA2
RA1
RA0
000
001
010
011
100
101
110
111
Total
Divide
Value
8
64
128
256
512
1024
1160
2048
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the ÷ N
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only a
SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that
require a logic 0 on the MC output (see Dual–Modulus Pres-
caling section). The A inputs all have internal pull–up resis-
tors that ensure that inputs left open will remain at a logic 1.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
OUTPUT PINS
φR,φV
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for
a loop–error signal.
If the frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC level
will be low at the beginning of a count cycle and will remain
low until the ÷ A counter has counted down from its pro-
grammed value. At this time, MC goes high and remains high
until the ÷ N counter has counted the rest of the way down
from its programmed value (N – A additional counts since
both ÷ N and ÷ A are counting down during the first portion of
the cycle). MC is then set back low, the counters preset to
Page 6 of 35
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Issue A

6 Page









ML145155 pdf, datenblatt
ML145155
www.DataSheet4U.com
FM ML12019
OSC ÷20 PRESCALER
AM
OSC
KEYBOARD
ML145155
2.56 MHz
LANSDALE Semiconductor, Inc.
fin
ML145155
φR
φV
DATA CLK ENB
CMOS
MPU/MCU
+ 1/2 MC1458*
TO
AM/FM
OSCILLATORS
TO DISPLAY
* The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
Figure 2. AM/FM Radio Synthesizer
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Issue A

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