PDF ML145152 Data sheet ( Hoja de datos )

Número de pieza	ML145152
Descripción	(ML145151 - ML145158) Parallel-Input PLL Frequency Synthesizer Interfaces
Fabricantes	LANSDALE Semiconductor
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No Preview Available ! www.DataSheet4U.com ML145151 ML145156 ML145152 ML145157 ML145155 ML145158 PLL Frequency Synthesizer Family - CMOS The devices described in this document are typically used as low–power, phase–locked loop frequency synthesizers. When combined with an external low–pass filter and voltage–controlled oscillator, these devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used between the VCO and the synthesizer IC. These frequency synthesizer chips can be found in the following and other applications: CATV TV Tuning AM/FM Radios Scanning Receivers Two–Way Radios Amateur Radio OSC ÷R CONTROL LOGIC φ ÷ A ÷N ÷ P/P + 1 VCO OUTPUT FREQUENCY EXTERNAL COMPONENTS CONTENTS Page DEVICE DETAIL SHEETS ML145151 Parallel–Input, Single–Modulus ...........................................................................................2 ML145152 Parallel–Input, Dual–Modulus..............................................................................................5 ML145155 Serial–Input, Single–Modulus ..............................................................................................9 ML145156 Serial–Input, Dual–Modulus...............................................................................................13 ML145157 Serial–Input, Single–Modulus ............................................................................................17 ML145158 Serial–Input, Dual–Modulus...............................................................................................20 FAMILY CHARACTERISTICS Maximum Ratings..................................................................................................................................23 DC Electrical Characteristics.................................................................................................................23 AC Electrical Characteristics.................................................................................................................25 Timing Requirements.............................................................................................................................26 Frequency Characteristics ......................................................................................................................27 Phase Detector/Lock Detector Output Waveforms................................................................................27 DESIGN CONSIDERATIONS Phase–Locked Loop – Low–Pass Filter Design ....................................................................................28 Crystal Oscillator Considerations ..........................................................................................................29 Dual–Modulus Prescaling......................................................................................................................30 Page 1 of 35 www.lansdale.com Issue A 1 page www.DataSheet4U.com ML145152 Parallel-Input PLL Frequency Synthesizer Interfaces with Dual–Modulus Prescalers Legacy Device: Motorola/Freescale MC145152 The ML145152 is programmed by sixteen parallel inputs for the N and A counters and three input lines for the R counter. The device features consist of a reference oscillator, selectable–reference divider, two–output phase detector, 10–bit programmable divide–by–N counter, and 6–bit pro- grammable ÷ A counter. • Operating Temperature Range: TA = – 40 to 85°C • Low Power Consumption Through Use of CMOS Technology • 3.0 to 9.0 V Supply Range • On– or Off–Chip Reference Oscillator Operation • Lock Detect Signal • Dual Modulus/Parallel Programming • 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048 • ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63 • Chip Complexity: 8000 FETs or 2000 Equivalent Gates • See Application Note AN980 28 1 P DIP 28 = YP PLASTIC DIP CASE 710 28 1 SO 28W = -6P SOG PACKAGE CASE 751F CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 28 SO 28W MC145152P2 ML145152YP MC145152DW2 ML145152-6P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENT fin 1 VSS 2 VDD 3 RA0 4 RA1 5 RA2 6 φR 7 φV 8 MC 9 A5 10 N0 11 N1 12 N2 13 N3 14 28 LD 27 OSCin 26 OSCout 25 A4 24 A3 23 A0 22 A2 21 A1 20 N9 19 N8 18 N7 17 N6 16 N5 15 N4 Page 5 of 35 www.lansdale.com Issue A 5 Page LANSDALE Semiconductor, Inc. www.DataSheet4U.com ML145155 ML145155 OUTPUT PINS PDout Phase Detector A Output (PDIP, SOG – Pin 6) Three–state output of phase detector for use as loop error signal. Double–ended outputs are also available for this pur- pose (see φV and φR). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High–Imped- ance State φR, φV Phase Detector B Outputs (PDIP, SOG – Pins 4, 3) These phase detector outputs can be combined externally for a loop–error signal. A single–ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by fV pulsing low. fR remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by fR pulsing low. fV remains essentially high. If the frequency of fV = fR and both are in phase, then both fV and fR remain high except for a small minimum time peri- od when both pulse low in phase. LD Lock Detector Output (PDIP – Pin 8, SOG – Pin 9) Essentially a high level when loop is locked (fR, fV of same phase and frequency). LD pulses low when loop is out of lock. SW1, SW2 Band Switch Outputs (PDIP – Pins 13, 14; SOG – Pins 14, 15) SW1 and SW2 provide latched open–drain outputs corre- sponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as 15 V, independent of the VDD supply voltage. These are typically used for band switch functions. A logic 1 causes the output to assume a high–impedance state, while a logic 0 causes the out- put to be low. REFout Buffered Reference Oscillator Output (PDIP, SOG – Pin 15) Buffered output of on–chip reference oscillator or externally provided reference–input signal. POWER SUPPLY VDD Positive Power Supply (PDIP, SOG – Pin 5) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (PDIP, SOG – Pin 7) The most negative supply potential. This pin is usually ground. UHF/VHF TUNER OR CATV FRONT END TYPICAL APPLICATIONS 4.0 MHz MC120xx PRESCALER KEYBOARD fin ML145155 φR φV DATA CLK ENB CMOS MPU/MCU 3 – + 1/2 MC1458* MC14489 LED DISPLAY * The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page for additional information.The φR and φV outputs swing rail–to–rail.Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface Page 11 of 35 www.lansdale.com Issue A 11 Page

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