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PDF ML14469 Data sheet ( Hoja de datos )
| Número de pieza | ML14469 | |
| Descripción | Addressable Asynchronous Receiver/Transmitter | |
| Fabricantes | LANSDALE Semiconductor | |
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Legacy Device: Motorola MC14469
ML14469
Addressable Asynchronous
Receiver/Transmitter
CMOS
The ML14469 receives one or two 11–bit words in a serial data
stream. One of the incoming words contains the address and when the
address matches, the ML14469 then transmits information in two
11–bit word data streams. Each of the transmitted words contains
eight data bits, an even parity bit, and start and stop bits.
The received word contains seven address bits with the address of
the ML14469 set on seven pins. Therefore, 27 or 128 units can be
interconnected in simplex or full–duplex data transmission. In addi-
tion to the address received, seven command bits may be received for
general–purpose data or control use.
The ML14469 finds application in transmitting data from remote
analog–to–digital converters, remote MPUs, or remote digital trans-
ducers to the master computer or MPU.
• Supply Voltage Range: 4.5 V to 18 V
• Low Quiescent Current: 75 µA Maximum @ 5 V, 25°C
• Guaranteed Data Rates to 4800 Baud @ 5 V, to 9600 Baud @ 12 V
• Receive — Serial to Parallel
Transmit — Parallel to Parallel
• Transmit and Receive Simultaneously in Full Duplex
• Crystal or Resonator Operation for On–Chip Oscillator
• See Application Note AN806A
• Chip Complexity: 1200 FETs or 300 Equivalent Gates
• Operating Temperature Range TA = –40° to +85°C
PIN ASSIGNMENTS
40
1
P DIP 16 = QP
PLASTIC DIP
CASE 711
PLCC 44 = -4P
PLCC PACKAGE
44
1
CASE 777
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 40
PLCC 44
MC14469P
MC14469FN
ML14469QP
ML14469-4P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
P DIP
OSC1
OSC2
RESET
A0
A1
A2
A3
A4
A5
A6
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
RI
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 C0
38 C1
37 C2
36 C3
35 C4
34 C5
33 C6
32 CS
31 VAP
30 SEND
29 S0
28 S1
27 S2
26 S3
25 S4
24 S5
23 S6
22 S7
21 TRO
PLCC
6 5 4 3 2 1 44 43 42 41 40
A2 7
39 C4
A3 8
38 C5
A4 9
37 C6
A5 10
36 CS
A6 11
35 VAP
NC 12
34 NC
ID0 13
33 SEND
ID1 14
32 S0
ID2 15
31 S1
ID3 16
30 S2
ID4 17
29 S3
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECTION
Page 1 of 10
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ML14469
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LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
A0 – A6
Address Inputs
These inputs are the address setting pins which contain the
address match for the received signal. Pins A0 – A6 have
on–chip pull–up resistors.
C0 – C6
Command Word
These pins are the readout of the general–purpose command
word which is the second word of the received signal.
CS
Command Strobe
This is the output for the command strobe signifying a valid
set of command data (C0 – C6). The pulse width is one oscil-
lator cycle. For example, when a 307.2 kHz ceramic resonator
is used, the pulse width is approximately 3 µs.
ID0 – ID7
Input Data Pins
These pins contain the input data for the first eight bits of
data to be transmitted. Pins ID0 – ID7 have on–chip pull–up
resistors.
OSC1, OSC2
Oscillator Input and Oscillator Output
These pins are the oscillator input and output (see Figure3).
RESET
Reset
When this pin is pulled low for a minimum of 700 ns, the
circuit is reset and ready for operation.
RI
Receive Input
This is the receive input pin.
S0 – S7
Second or Status Input Data
These pins contain the input data for the second eight bits of
data to be transmitted.
SEND
Send
This pin accepts the send command after receipt of an
address.
TRO
Transmit Register Output Signal
This pin transmits the outgoing signal. Note that it is invert-
ed from the incoming signal. It must go through one stage of
inversion if it is to drive another ML14469.
VAP
Valid Address Pulse
This is the output for the valid address pulse upon receipt of
a matched incoming address.
VDD
Positive Power Supply
This pin is the package positive power supply connection.
This pin may range from + 4.5 V to + 18 V with respect
toVSS.
VSS
Negative Power Supply
This pin is the negative power supply connection. Normally
this pin is system ground.
OPERATING CHARACTERISTICS
The receipt of a start bit on the receive input (RI) line causes
the receive clock to start at a frequency equal to that of the
oscillator divided by 64. All received data is strobed in at the
center of a receive clock period. The start bit is followed by
eight data bits. Seven of the bits are compared against states of
the address of the particular circuit (A0 –A6). Address is
latched 31 clock cycles after the end of the start bit of the
incoming address. The eighth bit signifies an address word “1”
or a command word “0”. Next, a parity bit is received and
checked by the internal logic for even parity. Finally a stop bit
is received. At the completion of the cycle if the address
matches, a valid address pulse (VAP) occurs. Immediately fol-
lowing the address word, a command word is received. It also
contains a start bit, eight data bits, even parity bit, and a stop
bit. The eight data bits are composed of a seven–bit command,
and a “0” which indicates a command word. At the end of the
command word a command strobe pulse (CS) occurs.
A positive transition on the send input initiates the transmit
sequence. Send must occur within seven bit times of CS. Again
the transmitted data is made up of two eleven–bit words, i.e.,
address and command words. The data portion of the first
word is made up from input data inputs (ID0 –ID7), and the
data for the second word from second input data (S0 – S7)
inputs. The data on inputs ID0 – ID7 is latched one clock
before the falling edge of the start bit. The data on inputs S0 –
S7 is latched on the rising edge of the start bit. The transmitted
signal is the inversion of the received signal, which allows the
use of an inverting amplifier to drive the lines. TRO begins
either 1/2 or 1–1/2 bit times after send, depending where send
occurs.
The oscillator can be crystal controlled or ceramic resonator
controlled for required accuracy. OSC1 can be driven from an
external oscillator (see Figure 3).
Page 5 of 10
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