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SD-146222x-xs Schematic ( PDF Datasheet ) - DDC

Teilenummer SD-146222x-xs
Beschreibung 2-Channel Synchro / Resolver to Digital Converter
Hersteller DDC
Logo DDC Logo 




Gesamt 11 Seiten
SD-146222x-xs Datasheet, Funktion
www.DataSheet4U.com
SD-14620 SERIES
TWO-CHANNEL SYNCHRO/RESOLVER-
TO-DIGITAL (S/R-D) CONVERTERS
DESCRIPTION
The SD-14620 Series converters are small, low-cost, two-channel
hybrid Synchro- or Resolver-to-Digital converters based on a single-
chip monolithic. The SD-14620X“S” option offers synthesized refer-
ence circuitry to correct for phase shifts between the reference and
signal inputs. The two channels are independent but share the digital
output and +5 VDC power pins. The package is 54-pin ceramic, yet is
the size of a 28-pin DDIP.
Resolution programming allows selection of 10-, 12-, 14- or 16-bit
modes. This feature allows selection of either low-resolution for fast
tracking or higher resolution for higher accuracy.
The velocity outputs (VEL A, VEL B) of the SD-14620 Series, which can
be used to replace a tachometer, are ±4 V signals referenced to analog
ground.The SD-14620 Series also offers Built-In-Test outputs for each
channel (BIT-A, BIT-B). The converters are available with operating
temperature ranges of 0°C to +70°C, -40°C to +85°C and -55°C to
+125°C. MIL-PRF-38534 processing is available.
Make sure the next
Card you purchase
has...
®
FEATURES
Synthesized Reference Option
1 Minute Accuracy Available
(“S” Option only)
Single +5 V Power Supply
10-, 12-, 14- or 16-Bit Programmable
Resolution
Small 54-Pin Ceramic Package
BIT Output
Velocity Output Replaces
Tachometer
High Reliability Single Chip
Monolithic
-55°C to +125°C Operating
Temperature Range
MIL-PRF-38534 Processing Available
APPLICATIONS
With its low-cost, small size, high accuracy and versatile performance,
the SD-14620 Series converters are ideal for use in modern high-per-
formance military, commercial and position control systems. Typical
applications include radar antenna positioning, motor control, robotics,
navigation and fire control systems.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
© 1991, 1999 Data Device Corporation






SD-146222x-xs Datasheet, Funktion
www.DataSheet4U.com
BIT, (BUILT-IN-TEST)
This output is an active low logic line that will flag an internal fault
condition or LOS (Loss-Of-Signal). The internal fault detector
monitors the internal loop error and, when it exceeds approximate-
ly ±100 LSBs, will set the line to a logic 0. This condition will occur
during a large-step input and will reset to a logic 1 after the con-
verter settles out. (The BIT is filtered with a 500 µs delay.) BIT will
set for an overvelocity condition because the converter loop can not
maintain input/output sync. For the “S” option only, this output will
be active low for an LOR (Loss-Of-Reference) fault condition.
NO FALSE 180° HANGUP
The converter is designed to eliminate a “false 180° reading” dur-
ing instantaneous 180° step changes. This condition most often
occurs when the input is “electronically switched” from a Digital-
to-Synchro converter. If the “MSB” (or 180° bit) is “toggled” on
and off, a converter without the “false 180° hangup” feature may
fail to respond. The condition is artificial, as a “real” synchro or
resolver cannot change its output 180° instantaneously. The con-
dition is most often noticed during wraparound verification tests,
simulations, or troubleshooting.
SYNTHESIZED REFERENCE
The synthesized reference section (“S” option) eliminates errors
due to phase shift between the reference and signal inputs of up
to 45°. Quadrature voltages in a resolver or synchro are by def-
inition the resulting 90° fundamental signal in the nulled out error
voltage (e) in the converter. Due to the inductive nature of syn-
chros and resolvers, their output signals lead the reference input
signal (RH and RL). When an uncompensated reference signal is
used to demodulate the control transformer’s output, quadrature
voltages are not completely eliminated. As shown in FIGURE 1,
the converter synthesizes its own internal reference signal based
on the SIN and COS signal inputs. Therefore, the phase of the
synthesized (internal) reference is determined by the signal input,
resulting in reduced quadrature errors. The synthesized reference
circuit also eliminates the 180 degree false error null hang up.
switched on and off. For instance, a 1000 V transient can be gen-
erated when the primary of a CX or TX input is opened.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while the data is being trans-
ferred. Application of an inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds (maximum) after
the application of the low-going Inhibit pulse.
Output angle data is enabled onto the tri-state data bus in 16
bits. This Enable MSB (EM-A or EM-B) is used for the most sig-
nificant 8 bits and Enable LSB (EL-A or EL-B) is used for the
least significant bits. As shown in FIGURE 4, output data is valid
150 nanoseconds (maximum) after the application of a low-going
enable pulse. The tri-state data bus returns to the high imped-
ance state 100 nanoseconds (maximum) after the rising edge of
the enable signal.
FOR 90 V SYNCHRO INPUTS
S3
S1
S2
90 V
SYNCHRO
INPUT
CR1
CR2
CR3
S3
RH
HYBRID
S2
RL
S1
CR4
115 V
REF.
INPUT
CR1, CR2, AND CR3 ARE 1.5kE170CA, BIPOLAR TRANSIENT
VOLTAGE SUPRESSORS OR EQUIVALENT.
CR4 IS A 1.5kE200C.
FIGURE 2. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
INTERFACING
SOLID-STATE BUFFER PROTECTION - TRANSIENT
VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input imped-
ance is maintained with power off. The recurrent AC peak + DC
common-mode voltage should not exceed the values in TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 300 V specification listed in TABLE 1. These tran-
sients can destroy the thin-film input resistor network in the
hybrid. Therefore, 90 V L-L solid-state input modules may be
protected by installing voltage suppressors (See FIGURE 2).
Voltage transients are likely to occur whenever a synchro is
Data Device Corporation
www.ddc-web.com
6
INHIBIT
500 ns max
;; ;;;DATA
DATA
VALID
FIGURE 3. INHIBIT TIMING
EM OR EL
150 ns MAX
100 ns MAX
;;;; ;;DATA
HIGH Z
DATA
VALID
HIGH Z
FIGURE 4. ENABLE TIMING
SD-14620
M-03/06-0

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