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87C196MC Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 87C196MC
Beschreibung Industrial Motor Control Microcontroller
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 22 Seiten
87C196MC Datasheet, Funktion
www.DataSheet4U.com
8XC196MC
INDUSTRIAL MOTOR CONTROL
MICROCONTROLLER
87C196MC 16 Kbytes of On-Chip OTPROM
87C196MC ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM
80C196MC ROMless
Y High-Performance CHMOS 16-Bit CPU
Y 16 Kbytes of On-Chip OTPROM
Factory-Programmed OTPROM
Y 488 bytes of On-Chip Register RAM
Y Register to Register Architecture
Y Up to 53 I O Lines
Y Peripheral Transaction Server (PTS)
with 11 Prioritized Sources
Y Event Processor Array (EPA)
4 High Speed Capture Compare
Modules
4 High Speed Compare Modules
Y Extended Temperature Standard
Y Two 16-Bit Timers with Quadrature
Decoder Input
Y 3-Phase Complementary Waveform
Generator
Y 13 Channel 8 10-Bit A D with Sample
Hold with Zero Offset Adjustment H W
Y 14 Prioritized Interrupt Sources
Y Flexible 8- 16-Bit External Bus
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y Idle and Power Down Modes
The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush-
less motors The 8XC196MC is based on Intel’s MCS 96 16-bit microcontroller architecture and is manufac-
tured with Intel’s CHMOS process
The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor
control applications This peripheral allows for pulse width modulation three phase sine wave generation with
minimal CPU intervention It generates 3 complementary non-overlapping PWM pulses with resolutions of
0 125 ms (edge trigger) or 0 250 ms (centered)
The 8XC196MC has 16 Kbytes on-chip OTPROM ROM and 488 bytes of on-chip RAM It is available in three
packages PLCC (84-L) SDIP (64-L) and EIAJ QFP (80-L)
Note that the 64-L SDIP package does not include P1 4 P2 7 P5 1 and the CLKOUT pins
Operational characteristics are guaranteed over the temperature range of b40 C to a85 C
The 87C196MC contains 16 Kbytes on-chip OTPROM The 83C196MC contains 16 Kbytes on-chip ROM All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted
OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package
and cannot be erased It is user programmable
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
April 1994
Order Number 270946-005






87C196MC Datasheet, Funktion
www.DataSheet4U.com
8XC196MC
NOTE
NC means No Connect Do not connect these pins
Figure 4 80-Lead Shrink EIAJQFP (Quad Flat Pack)
270946 – 4
6

6 Page









87C196MC pdf, datenblatt
www.DataSheet4U.com
8XC196MC
AC ELECTRICAL CHARACTERISTICS (Continued)
Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz
The 87C196MC will meet the following timing specifications
Symbol
Parameter
Min Max
TXHCH
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
TLLWL
TCLWL
TQVWH
TCHWH
TWLWH
TWHQX
TWHLH
TWHBX
TWHAX
TRHBX
TRHAX
XTAL1 to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Falling Edge
Address Hold after ALE Falling
ALE Falling Edge to RD Falling
RD Low to CLKOUT Falling Edge
RD Low Period
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
ALE Falling Edge to WR Falling
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE INST Hold after WR Rising
AD8–15 Hold after WR Rising
BHE INST Hold after RD Rising
AD8–15 Hold after RD Rising
30 110
2 TOSC
TOSC b 10
TOSC a 15
b5 15
b20
15
4 TOSC
TOSC b 10
TOSC a 10
TOSC b 15
TOSC b 40
TOSC b 30
4 30
TOSC b 5
TOSC
TOSC a 25
TOSC a 25
5
TOSC b 10
0
25
TOSC b 23
b10
15
TOSC b 30
TOSC b 25
TOSC b 10
TOSC b 10
TOSC b 30
TOSC b 10
TOSC b 30
TOSC a 15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3
3
1
3
1
2
2
NOTES
1 Assuming back to back cycles
2 8-bit bus only
3 If wait states are used add 2 TOSC N where N e number of wait states
12

12 Page





SeitenGesamt 22 Seiten
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