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D75206CW Schematic ( PDF Datasheet ) - NEC

Teilenummer D75206CW
Beschreibung upD75206
Hersteller NEC
Logo NEC Logo 




Gesamt 62 Seiten
D75206CW Datasheet, Funktion
www.DataSheet4U.com
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75206
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75206 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM,
I/O ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting
14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip.
It uses the VCR, ECR and CD fluorescent display tubes as display devices and is most suitable for applications
requiring the timer/watch function and high-speed interrupt servicing. It can help to provide the unit with many
functions and to decrease performance costs.
With the µPD75206, the µPD75P216A, 75P218 one-time PROM products are available for system development
evaluation or small production.
5
Detailed functions, etc. are described in the following user's manual. Be sure to read the manual for designing.
µPD75216A User's Manual: IEM-988
FEATURES
Architecture equal to that of an 8-bit microcomputer
High-speed operation : Minimum instruction execution time : 0.95 µs (when operated at 4.19 MHz)
Instruction execution time variable function realizing a wide range of operating voltages
On-chip large-capacity program memory : 6K bytes
Watch operation with an ultra low current consumption : 5µA TYP. (at the 3 V operation)
On-chip programmable fluorescent display tube controller/driver
Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
Interrupt function with importance attached to applications
• For power-off detection
• For remote controlled reception
Product with an on-chip PROM : µPD75P216A, µPD75P218 (on-chip EPROM : WQFN package)
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
5
5
µPD75206CW-×××
µPD75206GF-×××-3BE
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
Standard
Standard
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No. IC-1876A
(O. D. No. IC-6969C)
Date Published August 1993 P
Printed in Japan
The information in this document is subject to change without notice.
The mark 5 shows major revised points.
© NEC Corporation 1991






D75206CW Datasheet, Funktion
TI0/P13
PPO
SI/P03
SO/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
TIMER/PULSE
GENERATOR
INTTPG
SERIAL
INTERFACE
INTSIO
INTERRUPT
CONTROL
PROGRAM
COUNTER(13)
ROM
PROGRAM
MEMORY
6016 x 8 BITS
ALU
DECODE
AND
CONTROL
CY SP(8)
BANK
GENERAL REG.
RAM
DATA MEMORY
369 × 4 BITS
INTW
WATCH
TIMER
fX/2N
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
SUB MAIN
STAND BY
CONTROL
CPU CLOCK
Φ
BUZ/P23
XT1 XT2 X1 X2
VDD VSS RESET
PORT0
PORT1
4 P00–P03
4 P10–P13
PORT2
PORT3
PORT4
PORT5
PORT6
4 P20–P23
4 P30–P33
4 P40–P43
4 P50–P53
4 P60–P63
10 T0–T9
T10/PH3–
4 T13/PH0
FIP
CONTROLLER/
DRIVER
2
T14/S11,
T15/S10
10 S0–S9
VPRE
VLOAD
INTKS
PORTH
4 PH0–PH3

6 Page









D75206CW pdf, datenblatt
www.DataSheet4U.com
µPD75206
4. µPD75206 ARCHITECTURE AND MEMORY MAP
The µPD75206 has the following three architectural features.
Data memory bank configuration: Static RAM (320 words x 4 bits)
Display data memory (49 words x 4 bits)
Peripheral hardware (128 x 4 bits)
General register bank configuration: 8 x 4 banks (Operated in 4 bits)
4 x 4 banks (Operated in 8 bits)
Memory mapped I/O
Figures 4-1, 4-2 shows memory maps of µPD75206.
Fig. 4-1 Program Memory Map
Address
0000H
76
MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0 0 0 6 H MBE RBE
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0 0 0 E H MBE RBE
0020H
007FH
0080H
50
0 Internal Reset Start Address (Most Significant 5 Bits)
Internal Reset Start Address (Least Significant 8 Bits)
0 INTBT/INT4 Start Address (Most Significant 5 Bits) CALLF
INTBT/INT4 Start Address (Least Significant 8 Bits) !faddr
0 INT0 Start Address
(Most Significant 5 Bits) Instruction
INT0 Start Address
(Least Significant 8 Bits) Entry Address
0 INT1 Start Address
(Most Significant 5 Bits)
INT1 Start Address
(Least Significant 8 Bits)
0 INTSIO Start Address
(Most Significant 5 Bits)
INTSIO Start Address
0 INTT0 Start Address
INTT0 Start Address
0 INTTPG Start Address
INTTPG Start Address
0 INTKS Start Address
INTKS Start Address
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
BRCB
!caddr
Instruction
Branch Address
CALL !addr
Instruction
Subroutine Entry
Address
BR !addr
Instruction
Branch Address
GETI Instruction Reference Table
BR $addr Instruction
Relative Branch
Address
(-15 to -1 and +2 to +16)
07FFH
0800H
0FFFH
1000H
Branch Destination
Address and
Subroutine Entry
Address to be Set
by GETI Instruction
177FH
Remarks In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC
changed is enabled by BR PCDE and BR PCXA instructions.
12

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