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K9F1G08 Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K9F1G08
Beschreibung FLASH MEMORY
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 30 Seiten
K9F1G08 Datasheet, Funktion
www.DataSheet4U.com
K9F1G08Q0M K9F1G16Q0M
K9F1G08D0M K9F1G16D0M
K9F1G08U0M K9F1G16U0M
Document Title
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0 1. Initial issue
Draft Date
July. 5. 2001
Remark
Advance
0.1 1. Iol(R/B) of 1.8V is changed.
- min. value : 7mA --> 3mA
- Typ. value : 8mA --> 4mA
Nov. 5. 2001
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
3. A recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences as shown in Figure 17.
---> A recovery time of minimum 10µs is required before internal circuit gets
ready for any command sequences as shown in Figure 17.
Dec. 4. 2001
0.2 1. ALE status fault in ’Random data out in a page’ timing diagram(page 19)
is fixed.
0.3 1. tAR1, tAR2 are merged to tAR.(Page11)
(Before revision) min. tAR1 = 10ns , min. tAR2 = 50ns
(After revision) min. tAR = 10ns
2. min. tCLR is changed from 50ns to 10ns.(Page11)
3. min. tREA is changed from 35ns to 30ns.(Page11)
4. min. tWC is changed from 50ns to 45ns.(Page11)
5. tRHZ is devided into tRHZ and tOH.(Page11)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
6. tCHZ is devided into tCHZ and tOH.(Page11)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Apr. 25. 2002
0.4
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 35)
Nov. 22.2002
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 36)
0.5 1. The min. Vcc value 1.8V devices is changed.
K9F1GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 6.2003
0.6 Pb-free Package is added.
K9F1G08U0M-FCB0,FIB0
K9F1G08Q0M-PCB0,PIB0
K9F1G08U0M-PCB0,PIB0
K9F1G16U0M-PCB0,PIB0
K9F1G16Q0M-PCB0,PIB0
Mar. 13.2003
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1






K9F1G08 Datasheet, Funktion
www.DataSheet4U.com
K9F1G08Q0M K9F1G16Q0M
K9F1G08D0M K9F1G16D0M
K9F1G08U0M K9F1G16U0M
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9F1G08X0M)
I/O0 ~ I/O15
(K9F1G16X0M)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
PRE
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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K9F1G08 pdf, datenblatt
www.DataSheet4U.com
K9F1G08Q0M K9F1G16Q0M
K9F1G08D0M K9F1G16D0M
K9F1G08U0M K9F1G16U0M
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
1004
Typ.
-
Max
1024
Unit
Blocks
NOTE :
1. The K9F1GXXX0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
AC TEST CONDITION
(K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C
K9F1GXXQ0M : Vcc=1.70V~1.95V, K9F1GXXD0M : Vcc=2.4V~2.9V , K9F1GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F1GXXQ0M
K9F1GXXD0M
K9F1GXXU0M
Input Pulse Levels
0V to Vcc
0V to Vcc
0.4V to 2.4V
Input Rise and Fall Times
5ns 5ns
5ns
Input and Output Timing Levels
Vcc/2
Vcc/2
1.5V
K9F1GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9F1GXXD0M:Output Load (VccQ:2.65V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9F1GXXU0M:Output Load (Vcc:3.0V +/-10%)
K9F1GXXU0M:Output Load (Vcc:3.3V +/-10%)
-
- 1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
-
-
10 pF
10 pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
WP
HL L
HX
LHL
HX
HL L
HH
LHL
HH
LLL
HH
L L LH
X
XXXXHX
XXXXXH
XXXXXH
X X(1) X X X L
X X H X X 0V/VCC(2)
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
PRE
Mode
X Command Input
Read Mode
X Address Input(4clock)
X Command Input
Write Mode
X Address Input(4clock)
X Data Input
X Data Output
X During Read(Busy)
X During Program(Busy)
X During Erase(Busy)
X Write Protect
0V/VCC(2) Stand-by
12

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