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KS0108B Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer KS0108B
Beschreibung 64CH SEGMENT DRIVER
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 17 Seiten
KS0108B Datasheet, Funktion
www.DataSheet4U.com
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
INTRODUCTION
The KS0108B is a LCD driver LSl with 64 channel output
for dot matrix liquid crystal graphic display system. This
device consists of the display RAM, 64 bit data latch 64 bit
drivers and decoder logics. It has the internal display RAM
for storing the display data transferred from a 8 bit micro
controller and generates the dot matrix Iiquid crystal driv-
ing signals corresponding to stored data.The KS0108B
composed of the liquid crystal display system in combina-
tion with the KS0107B (64 common driver)
FEATURES
Dot matrix LCD segment driver with 64 channel output
Input and Output signal
- Input: 8 bit parallel display data
Control signal from MPU
Splitted bias voltage (V1R, V1L, V2R, V2L,
V3R. V3L, V4R, V4L)
- Output: 64 channel waveform for LCD driving.
Display data is stored in display data RAM from MPU.
Interface RAM
- Capacity: 512 bytes (4096 bits)
- RAM bit data: RAM bit data = 1:ON
RAM bit data- = 0:OFF
Applicable LCD duty: 1/32~1/64
LCD driving voltage: 8V~17V(VDD-VEE)
Power supply voltage: + 5V±10%
Driver
COMMON
SEGMENT
KS0107B Other KS0108B
Controller
MPU
High voltage CMOS process.
100QFP and bare chip available.
100 QFP






KS0108B Datasheet, Funktion
www.DataSheet4U.com
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC Characteristics(VDD=4.5~5.5V, VSS=0V, VDD-VEE=8~17V, Ta=-30~+85°C)
Characteristic
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Three-state(OFF) Input Current
Driver Input Leakage Current
Operating Current
On Resistance
Symbol
VIH1
VIH2
VIL1
VIL2
VOH
VOL
ILKG
ITSL
IDIL
IDD1
IDD2
RON
Condition
-
-
-
-
IOH=-200µA
IOL=1.6mA
VIN=VSS~VDD
VIN=VSS~VDD
VIN=VEE~VDD
During Display
During Access
Access Cycle=1MHz
VDD-VEE=15V
¡¾ILOAD=0.1mA
Min
0.7VDD
2.0
0
0
2.4
-
-1.0
-5.0
-2.0
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
VDD
VDD
0.3VDD
0.8
-
0.4
1.0
5.0
2.0
100
500
7.5
*1. CL, FRM, M, RSTB, CLK1, CLK2
2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7
3. DB0~DB7
4. Excepted DB0~DB7
5. DB0~DB7 at High lmpedance
6. V0L(R), V2L(R), V3L(R), V5L(R)
7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HZ, Output: No Load
8. VDD~VEE=15.5V
V0L(R)>V2L(R)=VDD-2/7 (VDD-VEE)>V3L(R)=VEE+2/7(VDD-VEE)>V5L(R)
AC Characteristics(VDD=5V±10%, VSS=0V, Ta=-30°C~+85°C)
(1) Clock Timing
Characteristic
CLK1, CLK2 Cycle Time
CLK1 LOWLevel Width
CLK2 LOWLevel Width
CLK1 HIGHLevel Width
CLK2 HIGHLevel Width
CLK1-CLK2 Phase Difference
CLK2-CLK1 Phase Difference
CLK1, CLK2 Rise Time
CLK1, CLK2 Fall Time
Symbol
tCY
tWL1
tWL2
tWH1
tWH2
tD12
tD21
tR
tF
Min
2.5
625
625
1875
1875
625
625
-
-
Typ
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
K
Max
20
-
-
-
-
-
-
150
150
Note
*1
*2
*1
*2
*3
*3
*4
*5
*6
*7
*7
*8
Unit
µS
ns

6 Page









KS0108B pdf, datenblatt
www.DataSheet4U.com
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
5. Busy flag
Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating.
When busy flag is low, KS0108B can accept the data or instruction.
DB7 indicates busy flag of the KS0108B.
6. Display On/Off Flip-Flop
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or
non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on
segment output terminals regardless of display RAM data.
The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low.
The status of the flip-flop is output to DB5 by status read instruction.
The display on/off flip-flop synchronized by CL signal.
7. X Page Register
X page register designates page of the internal display data RAM.
It has not count function. An address is set by instruction.
8. Y address counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased
by 1 automatically by read or write operations of display data.
9. Display Data RAM
Display data RAM stores a display data for liquid crystal display. To express on state dot matrix of liquid crystal display, write
data 1. The other way, off state writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
ADC=H¢¡ DB<0:7>=0 - Y-address 0 - A0 - S1
DB<0:7>=63 - Y-address 63 - A63 - S64
ADC=L¢¡ DB<0:7>=0 ~ Y-address 63 - A63 - S64
DB<0:7>=63 ~ A0 - S1
ADC terminal connect the VDD or VSS.
10. Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display.
Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred
to the Z address counter while FRM is high, presetting the Z address counter.
It is used for scrolling of the liquid crystal display screen.

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