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Z9973 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer Z9973
Beschreibung Multi-Output Zero Delay Buffer
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 9 Seiten
Z9973 Datasheet, Funktion
www.DataSheet4U.com
Z9973
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Features
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
TCLK0
TCLK1
TCLK_SEL
FB_IN
0
1
Phase
Detector
VCO
LPF
0
1
FB_SEL2
MR#/OE
Power-On
Reset
SELA(0,1)
2
SELB(0,1)
SELC(0,1)
2
2
FB_SEL(0,1)
2
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
0
/2 1
SCLK
SDATA
Output Disable
Circuitry
12
INV_CLK
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
Table 1. Frequency Table[1]
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FVC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
.
Pin Configuration
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7 Z9973 33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
SYNC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07089 Rev. *D
Revised December 21, 2002






Z9973 Datasheet, Funktion
www.DataSheet4U.com
Z9973
Maximum Ratings[3]
Maximum Input Voltage Relative to VSS: ............ VSS 0.3V
Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V
Storage Temperature: ................................65°C to + 150°C
Operating Temperature: ................................ 40°C to +85°C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD .
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = 40°C to +85°C)
Parameter
Description
Conditions
Min. Typ. Max. Unit
VIL
VIH
VPP
VCMR
IIL
IIH
VOL
VOH
IDDQ
IDDA
IDD
CIN
Input LOW Voltage
Input HIGH Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range PECL_CLK[9]
Input Low Current[10]
Input High Current[10]
Output Low Voltage[11]
Output High Voltage[11]
IOL = 20 mA
IOH = 20 mA
Quiescent Supply Current
PLL Supply Current
Dynamic Supply Current
Input Pin Capacitance
VDD only
QA and QB @ 60 MHz,
QC @ 120 MHz, CL = 30 pF
QA and QB @ 25 MHz,
QC @ 50 MHz, CL = 30 pF
VSS 0.8 V
2.0
VDD
V
300 1000 mV
VDD 2.0
VDD 0.6
120
120
0.5
2.4
10 15
15 20
225
V
µA
µA
V
V
mA
mA
mA
125
4 pF
AC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = 40°C to +85°C) [4]
Parameter
Description
Conditions
Min. Typ.
Tr / Tf
TCLK Input Rise / Fall
Fref Reference Input Frequency
Note 5
FrefDC
Reference Input Duty Cycle
25
Fvco
PLL VCO Lock Range
200
Tlock
Tr / Tf
Maximum PLL Lock Time
Output Clocks Rise/Fall Time[6]
0.8V to 2.0V
0.15
Notes:
3. The voltage on any input or I/O pic cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Parameters are guaranteed by design and characterization. Not 100% tested in production.
5. Maximum and minimum input reference is limited by VC0 lock range.
6. Outputs loaded with 30 pF each.
Max. Units
3.0 ns
Note 5 MHz
75 %
480 MHz
10 ms
1.2 ns
Document #: 38-07089 Rev. *D
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