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PDF LC78637E Data sheet ( Hoja de datos )
| Número de pieza | LC78637E | |
| Descripción | CMOS IC | |
| Fabricantes | Sanyo Electric | |
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LC78637E
CMOS IC
for Compact Disc Player Applications
Overview
The LC78637E combines audio CD RF signal processing, servo control, EFM signal processing, audio
signal processing, and a CDTEXT decoder in a single chip, enabling a system to be configured with very
few peripheral components. The RF signal processing block performs such functions as EFM signal
generation, error signal generation, and laser power control. The servo control block carries out A/D
conversion of focus error and tracking error signals from the RF signal processing block, and digitally
performs focus, tracking, sled, and spindle servo processing necessary for CD servo operation. The
functions of the EFM signal processing block cover EFM signal demodulation and synchronization
detection, protection, and interpolation, de-interleaving, and error detection and correction. The audio signal
processing block handles data interpolation/mute processing based on the error correction situation, and
incorporates an 8X over sampling filter, 1-bit DAC, and secondary LPF (differential amplifier). The status
and characteristics of each function block can be set, or ascertained by data reads, via the microcomputer
interface.
Playback functions
— Playback speed: 1X speed, 2X speed
— Jitter-free playback (VCEC)
— CD-R/W: 1X speed, 2X speed
— Simple CLV playback
RF processing block
— RF system: AGC, CD-R, R/W playback supported, peak hold, bottom hold
— Error system: Variable-balance TE signal generation, FE signal generation
— Detection: Track counting signal, jitter, flaws (black, mirror)
— Laser power control
— DC offset voltage cancellation
Servo control block
— Digital processing of tracking, focus, sled, and spindle servos
— Automatic adjustment functions: Focus gain, focus bias, focus offset, tracking gain, tracking offset,
tracking balance
— Use of Sanyo’s original high-performance servo control technology* to improve playability, covering
external vibration and playback of warped or eccentric discs
— Shock detection
— Interruption detection
* Robust control technology developed by Sanyo, offering remarkable ability to suppress vibration
and shocks, and to achieve tracking of warped or eccentric discs
EFM processing block
— Error detection and correction
(C1 = twofold, C2 = fourfold/twofold)
— Jitter margin: ± 13 frames
— DOUT output
— Built-in text decoder
— EFM signal synchronization detection,
protection, interpolation
Audio processing block
— Interpolation (4 interpolations)
— Digital attenuator
— Built-in de-emphasis filter
— 1-bit DAC (tertiary ∆ Σ noise shaper system)
— Built-in 8X oversampling digital filter
— Fadeout function
— Bilingual function
— Built-in secondary LPF for audio output
— DF and DAC clocks can be supplied externally
1 page  
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LC78637E
Absolute Maximum Ratings/Ta = 25 °C, Vss = 0 V
Item
Maximum power supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating ambient temperature
Storage ambient temperature
Symbol
VDD3max
VDD5max
VIN3
VIN5
VOUT3
VOUT5
Pdmax
Topg
Tstg
Conditions
Rating
VSS–0.3 to VSS+4.0
VSS–0.3 to VSS+6.0
VSS–0.3 to VDD3+0.3
VSS–0.3 to VDD5+0.3
VSS–0.3 to VDD3+0.3
VSS–0.3 to VDD5+0.3
540
–20 to +75
–40 to +125
Unit
V
V
V
V
V
V
mW
°C
°C
Allowable Operating Ranges/Ta = 25 °C, Vss = 0 V
Item
Power supply voltage
“H” level input voltage
“L” level input voltage
Data/CE setup time
Data/CE hold time
“H” level clock pulse width
“L” level clock pulse width
Data read access time
Command sending time
RAM read command sending
time
Subcode read cycle time
Subcode read enable time
Port input data setup time
Port input data hold time
Port output data delay time
Operating frequency range
Crystal oscillation frequency
Symbol
VDD3
VDD5
VIH3(1)
VIH3(2)
VIH5(1)
VIH5(2)
VIL3(1)
VIL3(2)
VIL5(1)
VIL5(2)
tSU
tHD
tWH
tWL
tRAC
tCE
tCERAM
tSC
tSE
tCSU
tCHD
tCDD
fOP
fX
Pin Name
Conditions
VDD, XVDD, LVDD, RVDD, VVDD,
AVDD1, AVDD2
VDD5
SBCK/FG, CONT4 to 5,
SBCK/CONT6, TEST,
ASLRCK, ASDATA, ASDFIN
EFMIN
CE, CL, DI, *RES
CONT1 to 3
SBCK/FG, CONT4 to 5,
SBCK/CONT6, TEST,
ASLRCK, ASDATA, ASDFIN
EFMIN
CE, CL, DI, *RES
CONT1 to 3
CL, DI, CE
Fig. 1, 2
CL, DI, CE
Fig. 1, 2
SBCK/FG, SBCK/CONT6, CL Fig. 1, 2, 3
SBCK/FG, SBCK/CONT6, CL Fig. 1, 2, 3
DO, MONI5 (PW signal)
Fig. 1, 2, 3,
4
CE Fig. 1, 2
CE Fig. 2
MONI3 (SFSY signal)
MONI3 (SFSY signal)
CONT1 to CONT5,
SBCK/CONT6, CL
CONT1 to CONT5,
SBCK/CONT6, CL
CONT1 to CONT5,
SBCK/CONT6, CE
EFMIN
XIN, XOUT
Fig. 3
Fig. 3
Fig. 4
Fig. 4
Fig. 5
Min.
3.0
3.0
0.7VDD3
0.6VDD3
0.8VDD5
0.7VDD5
0
0
0
0
400
400
400
400
0
1
12
400
400
400
Typ.
3.3
136
16.9344
Max. Unit
3.6 V
5.5
VDD3
V
V
VDD3
VDD5
VDD5
0.2VDD3
V
V
V
V
0.4VDD3
0.2VDD5
0.3VDD5
400
V
V
V
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
1200 ns
10 MHz
MHz
-5-
5 Page 
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LC78637E
Pin State after
No. Pin Name I/O Reset
Function
41 LVDD —
—
42
LCHO
AO
LVDD /2
L channel D/A
converter
43 LVSS —
—
L channel power supply pin
L channel output pin
L channel ground pin. Must be connected to 0V.
44 RVSS —
—
45
RCHO
AO
LVDD /2
R channel D/A
converter
46 RVDD —
—
R channel ground pin. Must be connected to 0V.
R channel output pin
R channel power supply pin
47 XVDD —
—
Crystal oscillation power supply pin
48
49
XOUT
XIN
O
I
Oscillation
Oscillation
For crystal oscillation
16.9344 MHz resonator connection pins
50
FSX/16MIN I/O
Input mode
7.35 kHz synchronization signal output pin, or DF/DAC external clock input
pin
51 XVSS —
—
For crystal
oscillation
Crystal oscillation ground pin. Must be connected to 0V.
52 C2F O
H C2 flag output pin
53 EFLG O
L C1, C2 correction monitor pin
54 16MOUT O CLK output 16.9344 MHz output pin
55 ASLRCK I
56 ASDACK I
57 ASDFIN I
— L/R clock input pin. (Connect to 0 V when not used.)
—
For anti-shock
mode
Bit clock input pin. (Connect to 0 V when not used.)
— L/R channel data input pin. (Connect to 0 V when not used.)
58 LRSY O
L
L/R clock output pin
59 DATACK O
L For digital data output
Bit clock output pin
60 DATA O
L
L/R channel data output pin
61 CE I
—
Chip enable signal input pin
62 CL I
—
Data transfer clock input pin
63 DI I
— For microcomputer interface Data input pin
64 DO O
(H)
Data output pin (Nch open-drain output)
65 ∗WRQ O
H
Interrupt signal output pin
66 ∗RES I
— LC78637E IC reset input pin. Drive to “L” level at power-on.
67 DRF O
L Focus ON detection pin
68 VDD5 —
— Microcomputer interface power supply pin
69 VSS —
— Digital ground pin. Must be connected to 0 V.
70 CONT3 I/O Input mode General-purpose I/O pin 3 Controlled by command from microcomputer.
71 CONT2 I/O Input mode General-purpose I/O pin 2 When not used, set as input pin and connect to
72 CONT1 I/O Input mode General-purpose I/O pin 1 0V or set as output pin and leave open.
73 PDO1 O
—
Built-in VCO control phase comparator output pin 1
74 PDO2 O
—
Built-in VCO control phase comparator output pin 2
75 VVDD —
— For PLL Built-in VCO power supply pin
76 PCKIST AI
—
PDO1, PDO2 output current setting resistor connection pin
77 VVSS —
—
Built-in VCO ground pin. Must be connected to 0V.
78 SLCO AO
79 EFMIN AI
—
—
For slice level control
Slice level control output pin
RF signal input pin
80 RF AO — RF signal output pin
Note: The same potential must be applied to all power supply pins (AVDD1, AVDD2, VVDD, VDD, LVDD,
RVDD, XVDD).
Pins operating on microcomputer interface power supply pin (VDD5V):
CE (pin 61), CL (pin 62), DI (pin 63), DO (pin 64), *WRQ (pin 65), *RES (pin 66), DRF (pin 67),
CONT1 (pin 72), CONT2 (pin 71), CONT3 (pin 70)
-11-
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LC78637E.PDF ] | |
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