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STEL-2060C Schematic ( PDF Datasheet ) - Intel

Teilenummer STEL-2060C
Beschreibung 45Mbps Viterbi Decoder
Hersteller Intel
Logo Intel Logo 




Gesamt 19 Seiten
STEL-2060C Datasheet, Funktion
www.DataSheet4U.com
STEL-2060C/CR
Data Sheet
STEL-2060C/CR
45 Mbps
Viterbi Decoder
R






STEL-2060C Datasheet, Funktion
www.DataSheet4U.com
ADDR2-0
The 3-bit address bus is used to access the various I/O
functions, as shown in the Memory Map table, below. Note
that some addresses contain both Read and Write registers.
These read and write mode registers are separate and contain
different data.
WRITE
The Write input is used to write data to the microprocessor
data bus. It is active low and is normally connected to the
write line of the host processor.
READ
The Read input is used to read data from the microprocessor
data bus. It is active low and is normally connected to the
read line of the host processor.
CSEL
The Chip Select input can be used to selectively enable the
microprocessor data bus. It is active low.
INT
The Interrupt output indicates when the Period Counter in
the BER Monitor has completed a count period, and that a
new value of BERCT is ready to be read from addresses 0H
and 1H, when INT will go high for one symbol period.
INPUT (WRITE) FUNCTIONS
COUNT7-0
The 8-bit COUNT7-0 data defines the period (i.e., the number
of bits) used in the node synchronization circuit. The 8-bit
number N is used to set up a period of (256N + 256) internally,
where N is the value of COUNT7-0. If the renormalization
count exceeds the threshold value during a period of this
number of bits then an out-of-sync condition is declared (i.e.,
the output pin OOS is set high and AUTO pulses high).
Reset value 00H.
THR7-0
The 8-bit THR7-0 data defines the threshold for node
synchronization when EXTSEL is set low. The function is
identical to that of the THR7-0 input signal. Reset value 00H.
BPER23-0
The 24-bit BER Period data is used to set the period (number
of data bits) over which the mean BER is measured by the
BER Monitor. The period used is 1000 times the value of
BPER23-0. Reset value FFFFFFH.
Note: The BER Count function incorporated in the
STEL-2060CCC uses a counter to count the number of
thousands of bits received. When the value of this counter is
equal to the value written into BPER23-0 the number of errors
counted is dumped into the BERCT15-0 output register and
can be read from read addresses 0-1H. Simultaneously, both
the error and bit counters are reset and the process is restarted,
and an interrupt (INT) is generated to indicate that the new
value is ready to be read.
Since the default (reset) value of the BPER23-0 register is
FF FF FFH a potential problem occurs if the desired value is
not written into this register before the value of the counter
has already incremented past this value. If this is not done
the equality will not be detected until after the counter
overflows and increments to the desired value once again.
Even at the maximum rate of 45 Mbps this will take over 6
minutes and, at a more modest data rate, such as 1 Mbps, it
will take over 41/2 hours! In any case, the user can easily be
misled into believing that the circuit is not operating correctly
since the interrupts will not be generated as expected. It is
therefore imperative that the BPER23-0 value be written into
the STEL-2060CCC as soon as possible after a reset to ensure
that this condition does not take place. The maximum time
allowable is just less than the desired interrupt period itself,
since the counter begins counting right after the reset is
released.
e.g., if the desired interrupt period is one second, the
BPER23-0 value must be written within one second of the
reset. At a data rate of 1 Mbps the period would correspond
to 106 bits and the correct BPER23-0 value would be 103, or
00 03 E8H.
If, for some reason, it is not possible to do this, a dummy
value should first be written into the STEL-2060CCC. This
should be large enough so that, at the time of writing, the bit
counter will not have exceeded the dummy value. In this
way the first interrupt will be generated within a reasonable
period of time and the dummy value can then be overwritten
with the desired value. Again, care must be taken to ensure
that the BPER23-0 value written is greater than the
instantaneous counter value, otherwise the same problem
will occur.
e.g., in the above example, if it is not possible to write the
BPER23-0 value until 5 seconds after the reset, then a dummy
BPER23-0 value corresponding to >5 seconds, e.g., 6 seconds,
or 00 17 70H should first be written. The desired value of
00 03 E8H must then be written within one second of an
interrupt generated by the STEL-2060CCC, thereby ensuring
that the counter has not exceeded the new value at that time.
OUTPUT (READ) FUNCTIONS
BERCT15-0
The 16-bit Bit Error Count data represents the mean Bit Error
Rate over the period determined by the BER Period data
BPER23-0. The actual BER is given by:
BER =
8 x BERCT15-0
1000 x BPER23-0
The value will be updated each time the period counter
completes its count. Completion is indicated by the INT
output going high for one clock cycle. If the accumulator
overflows during a measurement period its output will be
caused to saturate at a value of FFFFH.
STEL-2060C
6

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STEL-2060C pdf, datenblatt
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PUNCTURED SYMBOL SEQUENCES
1. RATE 1/2 AND EXTERNAL DEPUNCTURING - SEQUENTIAL INPUTS (PARL = 0)
Rate
Symbol sequence (suffix is symbol number in sequence, all at G12-0 input)
SYMCKIN DCLKIN
1/2 G11 G21 G12 G22 G13 G23 (Not Punctured)
2/3 G11 G21 P2 G22 G13 G23 P4 G24 G15 G25 P6 G26
3/4 G11 G21 P2 G22 G13 P3 G14 G24 P5 G25 G16 P6 G17 G27
2D
2D
2D
0
0
0
4/5 G11 G21 P2 G22 P3 G23 P4 G24 G15 G25 P6 P6 G27 P7
5/6 G11 G21 P2 G22 G13 P3 P4 G24 G15 P5 G16 G26 P7 G27
2D
2D
0
0
6/7 G11 G21 P2 G22 P3 G23 G14 P4 P5 G25 G16 P6 G17 G27
2D
0
7/8 G11 G21 P2 G22 P3 G23 P4 G24 G15 P5 P6 G26 G17 P7
2D
0
2. RATE 1/2 AND EXTERNAL DEPUNCTURING - PARALLEL INPUTS (PARL = 1)
Rate Input
Symbol sequence (suffix is symbol number in sequence)
SYMCKIN DCLKIN
1/2 G12-0 G11 G12 G13 G14 G15 G16
G22-0 G21 G22 G23 G24 G25 G26
(Not Punctured)
2/3 G12-0 G11 P2 G13 P4 G15 P6 G17 P8 G19 P10
G22-0 G21 G22 G23 G24 G25 G26 G27 G28 G29 G210
3/4 G12-0 G11 P2 G13 G14 P5 G16 G17 P8 G19 G110
G22-0 G21 G22 P3 G24 G25 P6 G27 G28 P9 G210
4/5 G12-0 G11
P2
P3
P4 G15 P6
P7
P8 G19 P10
G22-0 G21 G22 G23 G24 G25 G26 G27 G28 G29 G210
5/6 G12-0 G11 P2 G13 P4 G15 G16 P7 G18 P9 G110
G22-0 G21 G22 P3 G24 P5 G26 G27 P8 G29 P10
6/7 G12-0 G11
P2
P3 G14 P5 G16 G17 P8
G22-0 G21 G22 G23 P4 G25 P6 G17 G28
P9 G110
P9 G210
7/8 G12-0 G11
P2
P3
P4 G15 P6 G17 G18 P9 P10
G22-0 G21 G22 G23 G24 P5 G26 P7 G28 G29 G210
D0
D0
D0
D0
D0
D0
D0
3. INTERNAL DEPUNCTURING - SEQUENTIAL INPUTS (PARL = 0)
Rate
1/2
2/3
3/4
7/8
Symbol sequence (suffix is symbol number in sequence, all at G12-0 input)
SYMCKIN DCLKIN
G11 G21 G12 G22 G13 G23 G14 G24 G15
G11 G21 G22 G13 G23 G24 G15 G25 G26
G11 G21 G22 G13 G14 G24 G25 G16 G17
G11 G21 G22 G23 G24 G15 G26 G17 G18
(Not Punctured)
G17 G27 G28
G27 G28 G19
G28 G29 G210
2D
3/2 D
4/3 D
8/7 D
0
D
D
D
4. INTERNAL DEPUNCTURING - PARALLEL INPUTS (PARL = 1)
Rate Input
Symbol sequence (suffix is symbol number in sequence)
1/2 G12-0 G11 G12 G13 G14 G15 G16 G17
G22-0 G21 G22 G23 G24 G25 G26 G27
(Not Punctured)
2/3 G12-0 G11 G22 G23 G15 G26 G27 G19 G210 G211
G22-0 G21 G13 G24 G25 G17 G28 G29 G111 G212
3/4 G12-0 G11 G22 G14 G25 G17 G28 G110 G211 G113 G214
G22-0 G21 G13 G24 G16 G27 G19 G210 G112 G213 G115
7/8 G12-0 G11 G22 G24 G26 G18 G29 G211 G113 G115 G216
G22-0 G21 G23 G15 G17 G28 G210 G112 G214 G215 G117
SYMCKIN DCLKIN
D0
3/4 D
D
2/3 D
D
4/7 D
D
STEL-2060C
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