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W83627SF Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83627SF
Beschreibung I/O
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W83627SF Datasheet, Funktion
W83627SF
www.DataSheet4U.net
W83627SF
WINBOND I/O
Publication Release Date: May 31, 2005
- 1 - Revision A1






W83627SF Datasheet, Funktion
W83627SF
1. GENERAL DESCRIPTION
The W83627SF is the new generation of Winbond's LPC I/O products. It features a whole new
interface, namely LPC (Low Pin Count) interface, which is supported in mainstream Intel chip-set.
This interface as its name suggests is to provide an economical implementation of I/O's interface with
lower pin count and still maintains equivalent performance as its ISA interface counterpart.
Approximately 40 pins are saved in LPC I/O comparing to ISA implementation. With this additional
freedom, we can implement more devices on a single chip as demonstrated in W83627SF's
integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no
BIOS or device driver update is needed except chip-specific configuration.
As Smart Card application is gaining more and more attention, W83627SF also implements a smart
card reader interface featuring Smart wake-up function. This smart card reader interface fully meets
the ISO7816 and PC/SC (Personal Computer/Smart Card Workgroup) standards. W83627SF
provides a minimum external components and lowest cost soultion for smart card applications.
The disk drive adapter functions of W83627SF include a floppy disk drive controller compatible with
the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data
rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide
range of functions integrated onto the W83627SF greatly reduces the number of components required
for interfacing with floppy disk drives. The W83627SF supports four 360K, 720K, 1.2M, 1.44M, or
2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83627SF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud
rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83627SF
provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting
NEC, RC-5, extended RC-5, and RECS-80 protocols).
The W83627SF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or
two external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95/98TM, which makes system resource allocation more efficient than ever.
The W83627SF provides functions that complies with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through PME# or PSOUT#
function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up.
The W83627SF also has auto power management to reduce the power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEYTM -2,
Phoenix MultiKey/42TM, or customer code.
The W83627SF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.
The W83627SF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide.
Moreover, W83627SF is made to meet the specification of PC2000/PC2001's requirement in the
power management: ACPI and DPM (Device Power Management).
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6 Page









W83627SF pdf, datenblatt
W83627SF
4.2 FDC Interface
SYMBOL
DRVDEN0
PIN
1
DRVDEN1
SMI#
IRQIN1
GP27
2
INDEX#
3
MOA#
DSB#
DSA#
MOB#
DIR#
STEP#
WD#
WE#
4
5
6
7
8
9
10
11
TRAK0#
13
WP#
14
I/O
OD24
OD12
OD12
INt
I/OD12t
INcs
OD24
OD24
OD24
OD24
OD24
OD24
OD24
OD24
INcs
INcs
FUNCTION
Drive Density Select bit 0.
Drive Density Select bit 1. (Default)
System Management Interrupt.
Interrupt channel input.
General purpose I/O port 2 bit 7.
This Schmitt-triggered input from the disk drive is active low
when the head is positioned over the beginning of a track
marked by an index hole. This input pin is pulled up
internally by a 1 Kresistor. The resistor can be disabled by
bit 7 of L0-CRF0 (FIPURDWN).
Motor A On. When set to 0, this pin enables disk drive 0.
This is an open drain output.
Drive Select B. When set to 0, this pin enables disk drive B.
This is an open drain output.
Drive Select A. When set to 0, this pin enables disk drive A.
This is an open drain output.
Motor B On. When set to 0, this pin enables disk drive 1.
This is an open drain output.
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
Step output pulses. This active low open drain output
produces a pulse to move the head to another track.
Write data. This logic low open drain writes pre-
compensation serial data to the selected FDD. An open
drain output.
Write enable. An open drain output.
Track 0. This Schmitt-triggered input from the disk drive is
active low when the head is positioned over the outermost
track. This input pin is pulled up internally by a 1 K
resistor. The resistor can be disabled by bit 7 of L0-CRF0
(FIPURDWN).
Write protected. This active low Schmitt input from the disk
drive indicates that the diskette is write-protected. This input
pin is pulled up internally by a 1 Kresistor. The resistor
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
-12-

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