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PDF JS28F160B3 Data sheet ( Hoja de datos )
| Número de pieza | JS28F160B3 | |
| Descripción | (JS28Fxxx) Advanced Boot Block Flash Memory | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel® Advanced Boot Block Flash
Memory (B3)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Features
• Flexible SmartVoltage Technology
— 2.7 V – 3.6 V read/program/erase
— 12 V VPP fast production programming
• 1.65 V – .5 V or 2.7 V – 3.6 V I/O option
— Reduces overall system power
• High Performance
— 2.7 V – 3.6 V: 70 ns max access time
• Optimized Block Sizes
— Eight 8-KB blocks for data, top or
bottom locations
— Up to 127 x 64-KB blocks for code
• Block Locking
— VCC-level control through Write Protect
WP#
• Low Power Consumption
— 9 mA typical read current
• Absolute Hardware-Protection
— VPP = GND option
— VCC lockout voltage
• Extended Temperature Operation
— –40 °C to +85 °C
• Automated Program and Block Erase
— Status registers
• Intel® Flash Data Integrator Software
—Flash Memory Manager
—System Interrupt Manager
—Supports parameter storage, streaming
data (for example, voice)
• Extended Cycling Capability
—Minimum 100,000 block erase cycles
• Automatic Power Savings Feature
—Typical ICCS after bus inactivity
• Standard Surface Mount Packaging
—48-Ball CSP packages
—40-Lead and 48-Lead TSOP packages
• Density and Footprint Upgradeable for
common package
—8-, 16-, 32-, and 64-Mbit densities
• ETOX™ VIII (0.13 µm) Flash
Technology
—16-Mbit and 32-Mbit densities
• ETOX™ VII (0.18 µm) Flash Technology
—16-, 32-, and 64-Mbit densities
• ETOX ™ VI (0.25µm) Flash Technology
—8-, 16-, and 32-Mbit densities
• Bo not use the x8 option for new designs
The Intel® Advanced Boot Block Flash Memory (B3) device, manufactured on the Intel 0.13 µm
and 0.18 µm technologies, is a feature-rich solution at a low system cost. The B3 device in x16 is
available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family is
available only in 40-lead TSOP and 48-ball µBGA* packages. For additional information about
this product family, see the Intel website: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
Order Number: 290580, Revision: 020
18 Aug 2005
1 page  
www.DataSheet4U.com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Revision
Number
-001
-002
-003
-004
-005
-006
Description
Original version
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
VIH and VILSpecification change (Section 4.4)
ICCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
5
5 Page 
www.DataSheet4U.com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.2
3.2.1
3.2.2
3.2.3
Memory Maps and Block Organization
The B3 flash memory device uses an asymmetrically blocked architecture, enabling system
integration of code and data within a single flash memory device. Each block can be erased
independently of other blocks up to 100,000 times. For the address locations of each block, see the
following memory maps:
• Table 4 “16-Mbit and 32-Mbit Word-Wide Memory Addressing Map” on page 11
• Table 5 “4-Mbit and 8-Mbit Word-Wide Memory Addressing Map” on page 14
• Table 6 “16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map” on page 15
• Table 7 “8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map” on page 20
• Table 8 “4-Mbit Byte Wide Memory Addressing Map” on page 23
Parameter Blocks
The B3 flash memory device architecture includes parameter blocks to facilitate storing frequently
updated small parameters (such as data traditionally stored in an EEPROM). The word-rewrite
functionality of EEPROMs can be emulated using software techniques. Each flash memory device
contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096 words) each.
Main Blocks
After the parameter blocks, the remainder of the flash memory array is divided into equal-size main
blocks (65,536 bytes/32,768 words) for data or code storage.
• The 8-Mbit flash memory device contains 15 main blocks.
• The 16-Mbit flash memory device contains 31 main blocks.
• The 32-Mbit memory device contains 63 main blocks.
• The 64-Mbit memory device contains 127 main blocks.
4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps
Table 4.
Size
(KW)
4
4
4
4
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot
Bottom Boot
16 Mbit
FF000-FFFFF
FE000-FEFFF
32 Mbit
Size
(KW)
1FF000-1FFFFF
1FE000-1FEFFF
32
32
FD000-FDFFF 1FD000-1FDFFF 32
FC000-FCFFF 1FC000-1FCFFF 32
8 Mbit
16 Mbit
32 Mbit
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-
1EFFFF
1E0000-
1E7FFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet JS28F160B3.PDF ] | |
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