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Número de pieza | LP0701 | |
Descripción | P-Channel Enhancement-Mode Lateral MOSFET | |
Fabricantes | Supertex Inc | |
Logotipo | ||
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LP0701
P-Channel Enhancement-Mode
Lateral MOSFET
Features
General Description
► Ultra-low threshold
► High input impedance
► Low input capacitance
► Fast switching speeds
► Low on-resistance
► Freedom from secondary breakdown
► Low input and output leakage
Applications
► Logic level interfaces
► Solid state relays
► Battery operated systems
► Photo voltaic drives
► Analog switches
► General purpose line drivers
These enhancement-mode (normally-off) transistors utilize a
lateral MOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors
and with the high input impedance and negative temperature
coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free
from thermal runaway and thermally induced secondary
breakdown. The low threshold voltage and low on-resistance
characteristics are ideally suited for hand held, battery
operated applications.
Ordering Information
Device
Package Options
8-Lead SOIC (Narrow Body)
TO-92
LP0701
LP0701LG-G
-G indicates package is RoHS compliant (‘Green’)
LP0701N3-G
BVDSS/BVDGS
(V)
-16.5
RDS(ON)
(Ω)
1.5
VGS(TH)
(max)
(V)
-1.0
ID(ON)
(min)
(A)
-1.25
Pin Configurations
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±10V
Operating and storage temperature -55°C to +150°C
Soldering temperature*
+300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
DD DD
G
S
NC
NC
8-Lead SOIC (LG)
SOURCE
DRAIN
GATE
TO-92 (N3)
Product Marking
YYWW
P0701
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC (LG)
SiLP
0701
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page LP0701
D
8
Note 1
(Index Area
D/2 x E1/2)
1
Top View
E
E1
A
A A2
A1
Seating
Plane
e
Side View
b
A
Note 1
h
θ1
L
L1
View B
h
L2 Gauge
Plane
Seating
θ Plane
View B
View A-A
Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
A A1 A2 b D E E1 e h L L1 L2 θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
0.25 0.40
0O 5O
Dimension
(mm)
NOM
-
-
-
-
4.90
6.00
3.90
1.27
BSC
-
-
1.04 0.25
REF BSC
-
-
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00*
0.50 1.27
8O 15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet LP0701.PDF ] |
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