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PDF NS16550A Data sheet ( Hoja de datos )
| Número de pieza | NS16550A | |
| Descripción | UART | |
| Fabricantes | National Semiconductor | |
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Accessing the NS16550A
UART in the PS 2 Model 50
60 70 and 80
National Semiconductor
Application Note 628
Martin S Michael
July 1989
INTRODUCTION
This paper reviews fundamental concepts of the Micro
Channel Architecture and their relation to the NS16550A
UART All 4 of the PS 2 personal computers reviewed use
the NS16550A for asynchronous serial communication
The first part is an overview of the PS 2 system board and
Micro Channel Architecture (MCA) in the Models 50 60 70
and 80 personal computers The next part explains the ba-
sic configuration and system initialization procedures for the
UART that occur after power-up The last part describes the
overall interrupt procedure and the advantages of using the
on-chip FIFOs of the NS16550A These explanations de-
scribe the CPU accesses to the UART via MCA Timing dia-
grams in the appendix show these accesses to the UART
OVERVIEW OF THE PS 2 MODEL 50 60 70 AND 80
SYSTEM ARCHITECTURE
The block diagram indicates a number of identical functions
that all system boards have (Figure 1) Each system CPU
has an 8 channel DMA Controller and an optional math co-
processor associated with it via the local bus The DMA
Controller emulates the dual 8237 DMA controllers found on
the IBM AT Additionally this DMA Controller provides Ex-
tended and Virtual Mode operation These modes allow it to
interface with various DMA slave devices and the CPU to
dynamically select the arbitration level for 2 of the DMA
channels A central arbitration point allows certain adapter
cards and system peripherals to compete for DMA trans-
fers These adapter cards must have the appropriate arbi-
tration and DMA logic
Buffers condition the bus signals from the system CPU and
send them directly to the Micro Channel Interface These
signals after further buffering reach the system memory
and the system peripherals The system ROM on the Mod-
els 50 and 60 also interfaces via these buffers to the 80286
CPU In the Models 70 and 80 the 128 kbyte ROM interfac-
es via the local bus to the 80386 CPU
The dynamic RAM is expandable on the system board or on
adapter cards DMA controller addressing capability limits
the total DRAM available on any of these systems to 16
Mbytes The maximum DRAM available on the various sys-
tem boards is
1 Model 50 Type 1 e 1 Mbyte Type 2 e 2 Mbytes
2 Model 60 e 1 Mbyte
3 Model 70 Type 1 or Type 2 e 6 Mbytes
4 Model 80 Type 1 e 2 Mbytes Type 2 e 4 Mbytes
Beyond the memory coprocessor and DMA there are a
number of major peripheral functions resident on the system
board These are
1 serial port (NS16550A)
2 video graphics controller
3 diskette controller
4 parallel port
5 keyboard and pointing device controller
6 CMOS clock and configuration RAM
7 dual interrupt controllers (16 channels)
8 timer (3 channels)
The configuration software for the serial port on the system
board restricts the addressing of the NS16550A to COM1
and COM2 on the Models 50 60 70 and 80 Adapter card
serial ports however may be assigned any 1 of the 8 base
I O addresses
Adding adapter cards extends the PS 2 functionality be-
yond the system board These cards plug into the Micro
Channel Bus connectors and conform to the MCA proto-
cols
OVERVIEW OF THE MICRO CHANNEL ARCHITECTURE
MCA functionality increases as the data bus width increases
from 16 to 32 bits Both bus widths support certain funda-
mental features regardless of the data bus width One of
these is a centralized arbitration controller that allows up to
16 devices to contend for the 8 available DMA channels
These devices compete based on an assigned priority level
for the DMA resource A ‘‘fairness’’ option allows lower pri-
ority devices to compete successfully for a DMA channel
even though higher priority devices may require a transfer
If the fairness option is enabled each device that has re-
ceived DMA service must wait until all other devices re-
questing the DMA have been serviced before they are al-
lowed to compete for the DMA resource again MCA fixes
the priority levels of the DMA channels except for channels
0 and 4 which the CPU can program to any priority level
The DMA channels are capable of both 8- and 16-bit trans-
fers
MCA also features level sensitive interrupts provides for
interrupt sharing and brings 11 of the 16 hardware interrupts
out to the Micro Channel Bus for the adapters to use The
last section of this paper describes interrupt handling in
more detail
Previous PC architectures used jumpers and switches to
configure the adapter cards MCA uses programmable con-
figuration registers on each adapter card instead This adds
to system flexibility by allowing automatic card configuration
via software
The Models 50 and 60 support 8- or 16-bit transfers over a
64 kbyte range of I O addresses and over a 16 Mbyte range
of memory addresses The Models 70 and 80 have all of
these capabilities and can execute 32-bit transfers over the
64 kbyte I O address range or the 4 Gbyte memory address
range
IBM PC PS 2 and MicroChannel are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL C 10456
RRD-B30M75 Printed in U S A
1 page  
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TABLE 1 Asynchronous Communication
Port Addresses
Name
I O Addr
Interrupt Comment
Serial 1
Serial 2
Serial 3
Serial 4
Serial 5
Serial 6
Serial 7
Serial 8
03f8 – 03ff
02f8 – 02ff
3220 – 3227
3228 – 322f
4220 – 4227
4228 – 422f
5220 – 5227
5228 – 522f
IRQ 4
IRQ 3
IRQ 3
IRQ 3
IRQ 3
IRQ 3
IRQ 3
IRQ 3
COM1
COM2
The system board description file restricts the addresses of
the system board NS16550A to either COM1 or COM2
Adapter card ADFs determine which addresses are avail-
able for the UARTs on the adapter cards Each adapter card
contains a set of registers in the adapter I O address space
from 0100 to 0107 hex and also at 94 and 96 hex Since
these registers are at identical locations on all adapter
cards the system decodes a unique signal for each card
when it needs to address these registers This unique signal
is called Card Setup bCD SETUP (n) These ten registers
in the adapter I O address space
1 Enable either the adapter card or the system board
2 Store the adapter card I D number
3 Record the selected card options
4 Store card initialization data contained in the ADF
5 Provide error status or a pointer to error status
The NMI error handler uses this error status when the
adapter card signals (via channel check CHCK) a serious
error The error must be one that threatens the continued
operation of the system (i e a parity error) One of the se-
lectable options that the POS registers store is the address
assigned to each UART on the adapter card
The UART and these POS registers may be accessed at
any time through the DOS Debug port I O utility This is
done by enabling the setup of a particular adapter card
through POS registers 0094 0102 hex and then transferring
the data to the assigned UART addresses The Debug utility
allows the adapter card configuration to be changed without
running the Configuration Utilities By not using the Configu-
ration Utilities the user can easily cause configuration con-
flicts and should be cautious IBM does not recommend this
method of access but is useful when testing new hardware
UART ACCESSES HARDWARE
Appendix A contains timing diagrams of accesses to the
NS16550A addressed as COM2 on an IBM Dual Asynchro-
nous Card Signals from the Micro Channel Bus access this
card The timing of these signals should be the same for all
PS 2 systems with MCA however the measurements in Ap-
pendix A were done on only the Model 50 and Model 80
The read pulse width is approximately 390 ns The write
pulse width is approximately 220 ns and the chip select set-
up time is approximately 290 ns The first two diagrams in
Appendix A illustrate the basic read and write accesses to
the UART The middle two diagrams illustrate ‘‘back-to-
back’’ write and read accesses to the Scratch Pad Register
in the UART The last two diagrams illustrate the initializa-
tion steps done during POST
INTERRUPT HANDLING AND USE OF THE FIFOS
Interrupts on the PS 2 Models 50 60 70 and 80 are level-
sensitive low active This differs from the positive edge-sen-
sitive interrupts on the IBM PCs XTs and ATs There are
several reasons for this change One of the main reasons is
interrupt sharing It is apparent from the serial port address-
es listed in Table 1 that 7 of the 8 serial ports will activate
IRQ 3 for interrupt service In an edge-sensitive system the
Interrupt Control Unit (ICU) will not record any interrupt edg-
es arriving after the first edge but before the first interrupt is
cleared This makes interrupt sharing in an edge-sensitive
system impossible unless each device sharing the interrupt
is sophisticated enough to only issue an interrupt when an-
other device hasn’t
In a level-sensitive system multiple open-collector devices
can hold the same interrupt line low until the CPU services
each one The only additional hardware required is an inter-
rupt pending latch on each adapter card so that the CPU
can identify the card with an active interrupt The CPU then
executes the appropriate service routine for that card This
normally clears the device interrupt The software then
sends an End of Interrupt (EOI) to the ICU If the same
interrupt is still pending (interrupt sharing) the CPU checks
the next card that could activate the interrupt signal for an
active interrupt pending bit If the bit is active the CPU serv-
ices the interrupt as described above It continues trying to
clear this interrupt by checking and servicing the cards left
in the chain until the interrupt clears or a higher priority
event occurs
Devices sharing the same interrupt level may have a lengthy
wait before the CPU can service their interrupts This can
have a significant impact on the performance of a serial
channel receiver Since the receiver has no immediate con-
trol over the arrival of the incoming data without CPU inter-
vention it must be able to store the data for a period longer
than the interrupt latency time of the CPU The NS16550A
has a provision for long interrupt latencies Both the receiver
and transmitter have 16-byte FIFOs The CPU enables
these FIFOs by writing an x1 hex to the third register (FCR)
of the UART All UARTs that have this FIFO capability will
set two indicator bits in their Interrupt Identification Register
(IIR)
Therefore the software must read a Cx hex from the third
register (IIR) of the UART before relying on the FIFOs The
receiver FIFO buffers incoming data As this receiver FIFO
fills it will activate an interrupt The CPU programs the level
of receiver FIFO ‘‘fullness’’ needed to trigger this interrupt
The CPU selects one of these interrupt trigger levels during
the UART initialization This programmable trigger level al-
lows the receiver FIFO to accommodate varying system in-
terrupt latency times When the receiver FIFO fills to this
trigger level the UART issues an interrupt
Another advantage of having the FIFOs on both the trans-
mitter and receiver is the reduction in the number of inter-
rupts the CPU must process The NS16550A with enabled
FIFOs can issue th the number of transmitter interrupts
to the CPU as compared to one with disabled FIFOs The
reduction in receiver interrupts is proportional to the number
of bytes stored in the FIFO before the programmed trigger
level is reached Handling fewer interrupts reduces the
amount of overhead the CPU needs to execute Using the
transmitter FIFO allows the CPU to send the same amount
of data while executing th the overhead
5
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Detail of Last Part of Initialization
Initialization Sequence
(Including SCR)
WR SCR AAH
RD SCR AAH
WR CCR 80H
WR DLH 00H
WR DLL 30H
WR LCR 03H
WR IER 00H
RD LSR 60H
RD MSR 00H
Check for 8250-B Part
Set Dlab
Set Baud to 2400
8 Data 1 Stop no Parity
Disable Intrs
Clear Status
Clear Status
11
TL C 10456 – 10
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NS16550A.PDF ] | |
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