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PDF NS16550A Data sheet ( Hoja de datos )
| Número de pieza | NS16550A | |
| Descripción | UART Design and Application Considerations | |
| Fabricantes | National Semiconductor | |
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The NS16550A UART
Design and Application
Considerations
National Semiconductor
Application Note 491
Martin S Michael
Daniel G Durich
July 1987
BACKGROUND
UARTs like other system components have evolved for
many years to become faster more integrated and less ex-
pensive The rise in popularity of the personal computer with
its focus and competition primarily centered on an architec-
ture introduced by IBM has driven both UART perform-
ance and software compatibility issues As transmission
rates have increased the amount of time the CPU has for
other tasks while handling an active serial channel has been
sharply reduced One byte of data received at 1200 baud
(8 3 ms) is received in th the time at 19 2 kbaud (520 ms)
Software compatibility among the PC-based UARTs is crit-
ical due to the thousands of existing programs which use
the serial channel and the new programs continually being
offered
Higher baud rates and compatibility requirements influence
new UART designs These two constraints result in UARTs
that are capable of higher data rates increasingly indepen-
dent of CPU intervention and providing more autonomous
features while maintaining software compatibility These
development paths have been brought together in a new
UART from National Semiconductor designated the
NS16550A
The NS16550A has all of the registers of its two predeces-
sor parts (INS8250 and NS16450) so it can run all existing
IBM PC XT AT RT and compatible serial port software In
addition it has a programmable mode which incorporates
new high-performance features Of course all of these ad-
vanced features are useful in any asynchronous serial com-
munications application regardless of the host architecture
The reader is assumed to be familiar with the standard fea-
tures of the NS16450 so this paper will concentrate mainly
on the new features of the NS16550A If the reader is unfa-
miliar with these UARTs it is advisable to start by reading
their data sheets
The first section reviews some of the design considerations
and the operation of the NS16550A advanced features The
second section shows an NS16550A initialization routine
written in 80286 assembly code with an explanation of the
routine The third section gives a detailed example of com-
munications drivers written to interface two NS16550As on
individual boards These drivers are written for use with Na-
tional Semiconductor’s DB32032 evaluation boards but can
be ported to any NS32032-based system containing an
NS32202 (ICU)
1 0 Design Considerations and
Operation of the New
UART Features
In order to optimize CPU UART data transactions the
UART design takes into consideration the following con-
straints
GNXTM is a trademark of National Semiconductor Corporation
IBM is a registered trademark of International Business Machines Corporation
VAXTM is a trademark of Digital Equipment Corporation
80286TM is a trademark of Intel Corporation
1 The CPU is usually much faster than the UART at trans-
ferring data A high speed CPU could transfer a byte of
data to from the UART in a minimum of 280 ns The
UART would take over 1800 times longer to transmit re-
ceive this data serially if it were operating at 19 2 kbaud
2 There is a finite amount of wasted CPU time due to
software overhead when stopping its current task to
service the UART (context switching overhead)
3 The CPU may be required to complete a certain portion
of its current task in a multitasking system before servic-
ing the UART This delay is the CPU latency time asso-
ciated with servicing the interrupt The amount of time
that the receiver can accept continuous data after it re-
quests service from the CPU constrains CPU latency
time
The design constraints listed above are met by adding two
FIFOs and specialized transmitter receiver support circuitry
to the existing NS16450 design The FIFOs are 16 bytes
deep one holds data for the transmitter the other for the
receiver (see Figure 1 ) Similarity between the FIFOs stops
with their size as each has been customized for special
FIGURE 1 Rx and Tx FIFOs
TL C 9313 – 1
transmitter or receiver functions Each has support circuitry
to minimize software overhead when handling interrupts
The NS16550A receiver optimizes the CPU UART data
transaction via the following features
1 The depth of the Receiver (Rx) FIFO ensures that as
many as 16 characters will be ready to transfer when
the CPU services the Rx interrupt Therefore the CPU
transfer rate is effectively buffered from the serial data
rate
2 The program can select the number of bytes required in
the Rx FIFO (1 4 8 or 14) before the UART issues an
interrupt This allows the software to modify the interrupt
trigger levels depending on its current task or loading It
also ensures that the CPU doesn’t continually waste
time switching context for only a few characters
C1995 National Semiconductor Corporation TL C 9313
RRD-B30M105 Printed in U S A
1 page  
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FIGURE 4 NS16550A Initialization and Driver Flowchart
TL C 9313 – 4
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TL C 9313 – 8
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NS16550A.PDF ] | |
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