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PDF RTL8801B Data sheet ( Hoja de datos )
| Número de pieza | RTL8801B | |
| Descripción | 2-Port Cable Transceiver / Arbiter Chip | |
| Fabricantes | Realtek Microelectronics | |
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RTL8801B
2-PORT 100/200/400MBPS
CABLE TRANSCEIVER/ARBITER CHIP
DATASHEET
Rev. 3.4
11 August 2003
Track ID: JATR-1076-21
1 page  
www.DataSheet4U.com
RTL8801B
Datasheet
1. General Description
The RTL8801B provides a two-port physical layer (PHY) function in a cable-based IEEE 1394-1995 and
IEEE P1394a network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission.
1. Data bits to be transmitted through the cable ports are received from the Link On 2/4/8 data lines
(D0-D8), and are latched internally in the RTL8801B in synchronization with the 49.152MHz system
clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216Mbps
as an outbound data-strobe information stream. During transmission, the encoded data is transmitted
on the twisted pair B (TPB) cable pair(s), and the encoded strobe information is transmitted on the
twisted pair A (TPA) cable pair(s).
2. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data information is received on the TPA cable pair,
and the encoded strobe information is received on the TPB cable pair. The received data-strobe
information is decoded to recover the received clock signal and the serial data bits. The serial data bits
are split into two nibbles, or four by two bits, and parallel transmitted (repeated) out of the other active
(connected) cable ports.
3. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states
during initialization and arbitration. The output of these comparators is used by the internal logic to
determine the arbitration status. The TPA channel monitors the incoming cable common-mode
voltage. The value of the common-mode voltage is used during arbitration to set the speed of the next
packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage
for the presence of a remotely supplied twisted-pair bias voltage. The presence or absence of this
common-mode voltage is used as an indication of cable connection status. The cable connection status
signal is internally debounced in the RTL8801B on a cable disconnect-to-connect. The debounced
cable connection status signal initiates a bus reset. On a cable disconnect-to-connect, a debounce delay
is incorporated. There is no delay on a cable disconnect.
2-Port 100/200/400Mbps Cable Transceiver/Arbiter Chip 1
Track ID: JATR-1076-21 Rev. 3.4
5 Page 
www.DataSheet4U.com
RTL8801B
Datasheet
6. Register Descriptions
Definitions and usage for each of the registers listed below are provided on this and the following pages.
6.1. PHY Register Map for the Cable Environment
Address
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
Table 2. PHY Register Map for the Cable Environment
01234567
RHB
IBR
Extended(7)
Max_speed
Link_active Contender
Resume_int ISBR
Physical_ID
Loop
Reserved
Reserved
Jitter
Pwr_fail
R PS
Gap_count
Total_ports
Delay
Pwr_class
Timeout Port_event Enab_accel Enab_multi
Reserved
Page_select
Reserved
Port_select
Register0 (page_select)
1111b
Register7 (page_select)
6.2. PHY Register Fields for the Cable Environment
Table 3. PHY Register Fields for the Cable Environment
Item
Size Type Power Reset Description
Value
Physical_ID 6
R
- The address of this node is determined during self-identification. A
value of 63 indicates a miss-configured bus and the link will not
transmit any packets.
R
1R
- When set to 1, indicates that this node is the root.
PS
1R
- Cable Power Status.
RHB
1 RW
0 Root Hold-off Bit.
When set to 1, instructs the PHY to attempt to become the root during
the next tree identify process.
IBR
1 RW
0 Initiate Bus Reset.
When set to 1, instructs the PHY to initiate a bus reset immediately
(without arbitration). This bit causes assertion of the reset state for
166µs and is self-clearing.
Gap_count
6 RW
3F Used to configure the arbitration timer setting in order to optimize gap
times according to the topology of the bus. IEEE 1394-1995 4.3.6
Extended
3R
7 This field has a constant value of seven, which indicates the extended
PHY register map.
Total_ports
5
R
3 The number of ports implemented by this PHY.
Max_speed
3
R
010 Indicates the maximum speed this PHY supports.
000: 98.304Mbps
001: 98.304, 196.608Mbps
010: 98.304, 196.608, 393.216Mbps
All other values are reserved for future definition.
Delay
4R
0 Worse case repeater delay, expressed as 144+ (delay*20) ns.
2-Port 100/200/400Mbps Cable Transceiver/Arbiter Chip 7
Track ID: JATR-1076-21 Rev. 3.4
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet RTL8801B.PDF ] | |
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