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PDF MSP8120 Data sheet ( Hoja de datos )
| Número de pieza | MSP8120 | |
| Descripción | Multi-service Security Processor | |
| Fabricantes | PMC-Sierra | |
| Logotipo |  |
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MSP8120www.DataSheet4U.com
Multi-service Security Processor
PRODUCT OVERVIEW
PMC-Sierra's MSP8120 Multi-service Security-enabled processor is
designed to meet the needs of networking, security appliances, and
network attached storage applications.
The MSP8120 integrates standards-based security hardware to accel-
erate internet protocol security (IPSec) and secure socket layer (SSL)
performance for security appliances, firewalls, networking, and
storage applications.
The MSP8120 is part of the MSP8100 Series of highly-integrated,
feature-rich products that incorporate the high performance, power-
efficient MIPS 34K core. The processor provides PCI, dual Ethernet,
ROM, Flash, DDR, and low-speed peripheral interfaces, which are
connected internally to the MIPS 34K core by a high-bandwidth multi-
service bus.
BENEFITS
• High-performance 400 MHz MIPS32 core enables demanding
packet processing and network security applications
• Highly integrated system-on-a-chip (SoC) solution simplifies board
design, reducing component and overall system cost
• Hardware IPSec processing frees up the CPU for other applications
• Optimized memory controller provides low latency, high bandwith
access to SDRAM (333 MHz DDR-2)
MSP8120 NETWORK SECURITY APPLICATION
Unprotected
Network
RMII
RMII
MSP8120
Ethernet
Switch
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Released
Product Brief
PRODUCT HIGHLIGHTS
INTEGRATED SECURITY SUBSYSTEM
• Integrated security subsystem:
• Dedicated 2-channel DMA controller for security packet processing
• IPSec engine:
• Supports all IPSec packet transforms and implements SSL packet
transforms
• Implements DES/3DES/AES crypto and SHA-1/MD-5 hash
algorithm support
• Integrated queue manager for intelligent buffer management
• Random number generator
MIPS 34K MICROPROCESSOR CORE
• Supports MIPS32 Release 2 instruction set
• 400 MHz operation
• 9-stage pipeline
• 64 Kbyte Instruction and Data caches
• MIPS16e Code Compression
• 32-bit address paths, 64-bit data paths to caches and external
interface
• DSP instruction set extensions
• EJTAG debug and off-chip trace support
PROGRAMMABLE MEMORY MANAGEMENT UNIT
• 8-entry Instruction TLB (ITLB) and Data TLB (DTLB)
• 32 dual-entry Joint TLB (JTLB)
• JTLBs are sharable under software control
USB 2.0 CONTROLLER AND PHY
• Both host and device mode of operation
• Supports low-speed (LS) operation (1.5 Mbit/s), full-speed (FS)
operation (12 Mbit/s) and hi-speed (HS) operation (480 Mbit/s)
SYSTEM INTERRUPT CONTROLLER
• Handles interrupts for on-chip peripherals and 8 external interrupts
• Supports up to 32 PCI message signaled interrupts (MSI)
Protected
LAN
Clients
PMC-2070368, Issue 1
© Copyright PMC-Sierra, Inc. 2007
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet MSP8120.PDF ] | |
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