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RD151TS501US Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer RD151TS501US
Beschreibung PLL clock generator series
Hersteller Renesas Technology
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Gesamt 7 Seiten
RD151TS501US Datasheet, Funktion
www.DataSheet4U.com
RD151TS501US
PLL clock generator series
REJ03D0897-0102
Rev.1.02
Apr 25, 2007
Description
RD151TS501US is phase-locked loop clock generator with high-performance. And RD151TS501US is low-jitters and
will enable high density mounting by shrink small-size package (SSOP-8).
Features
Input frequency:
Output frequency:
27.0 to 36.0 MHz
54.0 to 72.0 MHz (1 : 2), 67.5 to 72.0 MHz (1 : 2.5)
27.0 to 36.0 MHz (1 : 1), 33.75 to 36.0 MHz (1 : 1.25) (Selectable)
Key Specifications
Supply voltages: VDD = 2.7 to 3.6 V
Operating temperature = -10 to 75 °C
Cycle to cycle jitter = ±75 ps typ.
Clock output duty cycle = 50±5%
Stabilization time: 2ms max
Power-down mode is supported
Ordering Information
Part Name
Package Type
RD151TS501USE
SSOP-8 pin
Package Code
(Previous Package Code)
PVSP0008KA–A
(TTP-8DBV)
Package
Abbreviation
US
Taping
Abbreviation (Quantity)
E (3,000 pcs / Reel)
Pin Arrangement
VDD 1
8 DIV2
VDD 2
7 IN
VSS 3
6 SEL
OUT 4
(Top view)
5 PDWN
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 1 of 6






RD151TS501US Datasheet, Funktion
RD151TS501US
Package Dimensions
JEITA Package Code
P-VSSOP8-2.3x2-0.50
RENESAS Code
PVSP0008KA-A
Previous Code
MASS[Typ.]
TTP-8DB/TTP-8DBV
0.010g
D
1.5 ±0.2
85
F
1
e
4
bp
bp
b1
Terminal cross section
L1
Detail F
Reference Dimension in Millimeters
Symbol Min Nom Max
D 1.8 2.0 2.2
E 2.2 2.3 2.4
A2 0.6 0.7 0.8
A1 0
0.1
A
bp 0.15 0.22 0.3
b1 0.20
c 0.08 0.13 0.23
c1 0.11
θ
HE 2.8 3.1 3.4
e (0.5)
x
y
Z
L
L1 (0.4)
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 6 of 6

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