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U635H16 Schematic ( PDF Datasheet ) - Simtek

Teilenummer U635H16
Beschreibung PowerStore 2K x 8 nvSRAM
Hersteller Simtek
Logo Simtek Logo 




Gesamt 14 Seiten
U635H16 Datasheet, Funktion
www.DataSheet4U.com
Obsolete - Not Recommended for New Designs
U635H16
PowerStore 2K x 8 nvSRAM
Features
High-performance CMOS non-
volatile static RAM 2048 x 8 bits
25, 35 and 45 ns Access Times
12, 20 and 25 ns Output Enable
Access Times
ICC = 15 mA at 200 ns Cycle Time
Automatic STORE to EEPROM
on Power Down using system
capacitance
Software initiated STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
Unlimited RECALL cycles from
EEPROM
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Packages: PDIP24 (600 mil)
SOP24 (300 mil)
Description
The U635H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U635H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up. The U635H16 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 24
2 23
3 22
4 21
5 20
6 PDIP 19
7
SOP
24
18
8 17
9 16
10 15
11 14
12 13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0050
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0






U635H16 Datasheet, Funktion
U635H16
Write Cycle #1: W-controlledj
Ai
E
W
DQi
Input
DQi
Output
tcW (12)
Address Valid
tsu(E) (17)
th(A) (21)
tsu(A)
(15)
tsu(A-WH) (16)
tw(W) (13)
tsu(D) (19)
th(D) (20)
Input Data Valid
tdis(W) (22)
ten(W) (23)
Previous Data
High Impedance
Write Cycle #2: E-controlledj
Ai
E
W
DQi
Input
DQi
Output
tsu(A) (15)
tcW (12)
Address Valid
tw(E) (18)
th(A) (21)
tsu(W) (14)
tsu(D) (19)
th(D) (20)
Input Data Valid
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
STK Control #ML0050
6
Rev 1.0
March 31, 2006

6 Page









U635H16 pdf, datenblatt
U635H16
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read address 000 (hex) Valid READ
2. Read address 555 (hex) Valid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70E (hex) Initiate RECALL
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Hardware Protection
The U635H16 offers hardware protection against inad-
vertent STORE operation through VCC Sense. When
VCC < VSWITCH all software controllod STORE operati-
ons will be inhibited.
Low Average Active Power
The U635H16 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
STK Control #ML0050 12
Rev 1.0
March 31, 2006

12 Page





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