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AZ100LVEL16VV Schematic ( PDF Datasheet ) - Arizona Microtek

Teilenummer AZ100LVEL16VV
Beschreibung Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer
Hersteller Arizona Microtek
Logo Arizona Microtek Logo 




Gesamt 9 Seiten
AZ100LVEL16VV Datasheet, Funktion
www.DataSheet4U.com
ARIZONA MICROTEK, INC.
AZ100LVEL16VV
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
FEATURES
PACKAGE AVAILABILITY
High Bandwidth for 1GHz
Similar Operation as AZ100EL16VR
except with selectable data input pairs
Operating Range of 3.0V to 5.5V
Minimizes External Components
Available in a 3x3mm MLP Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona
Microtek Website
PACKAGE
PART NUMBER MARKING NOTES
MLP 16 (3x3) RoHS
AZM+
Compliant / Lead (Pb) AZ100LVEL16VVL+ 16K
1,2
Free <Date Code>
DIE
AZ100LVEL16VVXP N/A
3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2 Date code format: “Y” for year followed by “WW” for week.
3 Waffle Pack
DESCRIPTION
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain
output buffer including an enable. The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯
outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different
oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D¯¯0 is selected. When the
SEL pin is HIGH data from the D1/D¯¯1 is selected. Allowing continuous oscillator operation, the (EN) enable works
with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN
is LOW, the QHG/Q¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to
the Q/Q¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS
type logic signal.
The AZ100LVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately
connected to VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is
recommended.
Each Q/Q¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase
pull-down current of the Q/Q¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com






AZ100LVEL16VV Datasheet, Funktion
AZ100LVEL16VV
D0
D1
EN
SEL
Q
Q
QHG
QHG
TIMING DIAGRAM
PINOUTS FOR MLP16 PACKAGE
Q Q NC VCC
16 15 14 13
D0 1
12 SEL
D0 2
D1 3
MLP16
11 QHG
10 QHG
D1 4
9 EN
5 67 8
VBB NC VEE NC
Bottom Center Pad may be left open or tied to VEE
April 2007 * REV - 9
www.azmicrotek.com
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