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PDF MT47H32M8 Data sheet ( Hoja de datos )
| Número de pieza | MT47H32M8 | |
| Descripción | (MT47HxxMx) DDR2 SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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DDR2 SDRAM
256Mb: x4, x8, x16
DDR2 SDRAM
MT47H64M4–16 MEG X 4 X 4
MT47H32M8–8 MEG X 8 X 4
MT47H16M16–4 MEG X 16 X 4
For the latest data sheet, please refer to the Micron Web
site: http://www.micron.com/datasheets
Features
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• Duplicate output strobe (RDQS) option for x8
configuration
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Programmable CAS Latency (CL): 3 and 4
• Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
Options
• Configuration
64 Meg x 4 (16 Meg x 4 x 4)
32 Meg x 8 (8 Meg x 8 x 4)
16 Meg x 16 (4 Meg x 16 x 4)
• FBGA Package Lead-Free
x4x8
60-ball FBGA (8mm x 12mm)
x16
84-ball FBGA (8mm x 14)mm
• Timing – Cycle Time
5.0ns @ CL = 4 (DDR2-400)
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
Designation
64M4
32M8
16M16
BP
BG
-5
-5E
-37E
ARCHITECTURE 64 MEG X 4 32 MEG X 8 16 MEG X 16
Configuration 16 Meg x 4 x 4
Refresh Count
8K
Row Addressing 8K (A0-A12)
Bank Addressing 4 (BA0 - BA1)
Column
Addressing
2K (A0-A9, A11)
8 Meg x 8 x 4
8K
8K (A0-A12)
4 (BA0 - BA1)
1K (A0-A9)
4 Meg x 16 x 4
8K
8K (A0-A12)
4 (BA0 - BA1)
512K (A0-A8)
Table 1: Key Timing Parameters
SPEED
GRADE
-5
-5E
-37E
DATA RATE
(MHz)
CL = 3
–
400
400
CL = 4
400
400
533
tRCD
(ns)
20
15
15
tRP
(ns)
20
15
15
tRC
(ns)
65
55
60
09005aef80b12a05
256Mb_DDR2_1.fm - Rev. C 5/04 EN
1 ©2003 Micron Technology, Inc. All rights reserved.
1 page  
www.DataSheet4U.com
256Mb: x4, x8, x16
DDR2 SDRAM
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Figure 78:
Figure 79:
Figure 80:
Figure 81:
ODT timing for “Slow-Exit” or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ODT “Turn Off” Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
ODT “Turn-On” Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
ODT “Turn-Off” Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
ODT “Turn On” Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Nominal Slew Rate for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Tangent Line for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Nominal Slew Rate for tIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Tangent Line for tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
AC Input Test Signal Waveform Command/Address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
AC Input Test Signal Waveform for Data with DQS,DQS# (differential) . . . . . . . . . . . . . . . . . . . . . . . .82
AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
AC Input Test Signal Waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Full Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Package Drawing 60-Ball (8mmx12mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Package Drawing 84-Ball (8mmx14mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
09005aef80b12a05
DDR2_256MbLOF.fm - Rev. C 5/04 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
www.DataSheet4U.com
256Mb: x4, x8, x16
DDR2 SDRAM
Table 2: FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16
x16 FBGA x4, x8 FBGA
BALL
BALL
ASSIGNMENT ASSIGNMENT SYMBOL
TYPE DESCRIPTION
M8, M3, M7,
N2, N8, N3,
N7, P2, P8, P3,
M2, P7, R2
G8, G2, H7,
H3, H1, H9, F1,
F9, C8, C2, D7,
D3, D1, D9, B1,
B9
–
–
B7, A8
F7, E8
–
–
A1, E1, J9, M9,
R1
J1
A9, C1, C3, C7,
C9, E9, G1, G3,
G7, G9
J2
A3, E3, J3, N1,
P9
J7
A7, B2, B8, D2,
D8, E7, F2, F8,
H2, H8,
H8, H3, H7, J2,
J8, J3, J7, K2,
K8, K3, H2, K7,
L2
–
C8, C2, D7, D3,
D1, D9, B1, B9
C8, C2, D7, D3
–
–
B7, A8
B3, A2
A1, E9, H9, L1
E1
A9, C1, C3, C7,
C9
E2
A3, E3, J1, K9
E7
A7, B2, B8, D2,
D8
A0–A12
DQ0–
DQ15
DQ0–DQ7
DQ0–DQ3
UDQS,
UDQS#
LDQS,
LDQS#
DQS,
DQS#
RDQS,
RDQS#
VDD
VDDL
VDDQ
VREF
VSS
VSSDL
VSSQ
Input
I/O
I/O
I/O
I/O
I/O
I/O
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for Read/Write
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
Data Input/Output: Bidirectional data bus for 16 Meg x 16.
Data Input/Output: Bidirectional data bus for 32 Meg x 8.
Data Input/Output: Bidirectional data bus for 64 Meg x 4.
Data Strobe for Upper Byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Data Strobe for Lower Byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. LDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Data Strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data, center
aligned with write data. DQS# is only used when differential data
strobe mode is enabled via the LOAD MODE command.
Redundant Data Strobe for 32 Meg x 8 only. RDQS is enabled/
disabled via the LOAD MODE command to the Extended Mode
Register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled,
pin B3 becomes Data Mask (see DM pin). RDQS# is only used when
RDQS is enabled AND differential data strobe mode is enabled.
Power Supply: 1.8V ±0.1V
DLL Power Supply: 1.8V ±0.1V
DQ Power Supply: 1.8V ±0.1V. Isolated on the device for improved
noise immunity.
SSTL_18 reference voltage.
Ground.
DLL Ground. Isolated on the device from VSS and VSSQ.
DQ Ground. Isolated on the device for improved noise immunity.
09005aef80b12a05
256Mb_DDR2_2.fm - Rev. C 5/04 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT47H32M8.PDF ] | |
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