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AD5065 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5065
Beschreibung (AD5025 - AD5065) DAC SPI Interface
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD5065 Datasheet, Funktion
Fully Accurate, 12-/14-/16-Bit, Dual, VOUT
nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
AD5025/AD5045/AD5065
FEATURES
Low power dual 12-/14-/16-bit DAC, ±1 LSB INL
Individual voltage reference pins
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V
3 power-down functions
Per channel power-down
Low glitch upon power-up
Hardware power-down lockout capability
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-lead TSSOP
APPLICATIONS
Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit
buffered voltage output nanoDAC® DACs offering relative accuracy
specifications of ±1 LSB INL with individual reference pins, and
can operate from a single 4.5 V to 5.5 V supply. The AD5025/
AD5045/AD5065 also offer a differential accuracy specification of
±1 LSB. The parts use a versatile 3-wire, low power Schmitt
trigger serial interface that operates at clock rates up to 50 MHz
and is compatible with standard SPI®, QSPI™, MICROWIRE™,
and DSP interface standards. The reference for the AD5025/
AD5045/AD5065 are supplied from an external pin and a refer-
ence buffer is provided on chip. The AD5025/AD5045/AD5065
incorporate a power-on reset circuit that ensures the DAC output
powers up zero scale or midscale and remains there until a valid
write takes place to the device. The AD5025/AD5045/AD5065
contain a power-down feature that reduces the current consump-
tion of the device to typically 400 nA at 5 V and provides software
selectable output loads while in power-down mode. The parts are
put into power-down mode over the serial interface. Total unad-
justed error for the parts is <2.5 mV. The parts exhibit very low
glitch on power-up. The outputs of all DACs can be updated
simultaneously using the LDAC function, with the added
functionality of user-selectable DAC channels to simultaneously
update. There is also an asynchronous CLR that clears all DACs
to a software-selectable code—0 V, midscale, or full scale. The
parts also feature a power-down lockout pin, PDL, which can be
used to prevent the DAC from entering power-down under any
circumstances over the serial interface.
PRODUCT HIGHLIGHTS
1. Dual channel available in a 14-lead TSSOP package with
individual voltage reference pins.
2. 12-/14-/16-bit accurate, ±1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
7. Power-down lockout capability.
Table 1. Related Devices
Part No.
Description
AD5666
Quad,16-bit buffered DAC, 16 LSB INL, TSSOP
AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
AD5062/AD5063
16-bit nanoDAC, 1 LSB INL, MSOP
AD5061
16-bit nanoDAC, 4 LSB INL, SOT-23
AD5040/AD5060
14-/16-bit nanoDAC, 1 LSB INL, SOT-23
FUNCTIONAL BLOCK DIAGRAM
POR
VDD
VREFA VREFB
SCLK
SYNC
DIN
LDAC
SDO
LDAC
INPUT
REGISTER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC A
DAC B
PDL CLR
AD5025/AD5045/AD5065
Figure 1.
BUFFER
BUFFER
POWER-DOWN
LOGIC
GND
VOUTA
VOUTB
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






AD5065 Datasheet, Funktion
AD5025/AD5045/AD5065
SCLK
S YNC
DIN
LDAC1
LDAC2
CLR
VOUT
t8 t4
t1
t3 t2
t9
t7
DB31
t6
t5
DB0
t13
t10
t11
t12
t14
PDL
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t19
Figure 3. Serial Write Operation
SCLK
SYNC
DIN
t8 t4
DB31
t5
t6
32
DB0 DB31
64
t16
t17
DB0
SDO
LDAC1
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N + 1
t15
DB31
INPUT WORD FOR DAC N
CLR
PDL
1IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.
Figure 4. Daisy-Chain Timing Diagram
DB0
t18
t10
t18
t12
t18
t19
Rev. 0 | Page 6 of 28

6 Page









AD5065 pdf, datenblatt
AD5025/AD5045/AD5065
CH1 = SCLK
1
CH2 = VOUT
2
VDD = 5V
POWER-UP TO MIDSCALE
CH1 5V
CH2 500mV
M2µs
T 55%
A CH2 1.2V
Figure 24. Exiting Power-Down to Midscale
6
5
4
3
2
1
0
–1
–2
–3
0 2.5 5.0 7.5
TIME (μs)
Figure 25. Digital-to-Analog Glitch Impulse
10.0
7
6
VDD = 5V, VREF = 4.096V
TA = 25ºC
5
4
3
2
1
0
–1
–2
–3
–4
0 2.5 5.0 7.5
TIME (μs)
Figure 26. Analog Crosstalk
10.0
7
6
TVADD=
= 5V,
25°C
VREF
=
4.096V
5
4
3
2
1
0
–1
–2
–3
–4
0 2.5 5.0 7.5 10.0
TIME (μs)
Figure 27. DAC-to-DAC Crosstalk
VDD = 5V, VREF = 4.096V
TA = 25ºC
DAC LOADED WITH MIDSCALE
4s/DIV
Figure 28. 0.1 Hz to 10 Hz Output Noise Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5
VDD = 5V,
TA = 25ºC
DAC LOADED WITH MIDSCALE
VREF = 3.0V ± 200mV p-p
10 20 30 40
FREQUENCY (kHz)
Figure 29. Total Harmonic Distortion
50 55
Rev. 0 | Page 12 of 28

12 Page





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